MIPS: Enable movt, movz, movn and movf instructions on mips32r1

MIPS: Enable movt, movz, movn and movf instructions on mips32r1

Committed: https://crrev.com/d40445884939341c33a78d64962686ddee2a733e
Cr-Commit-Position: refs/heads/master@{#32054}

[Djordje.Pesic, 2015-11-16 07:20:40]

Description was changed from

==========
MIPS: Enable movt, movz, movn and movf instructions on mips32r1

BUG=
==========

to

==========
MIPS: Enable movt, movz, movn and movf instructions on mips32r1

BUG=
==========

[Djordje.Pesic, 2015-11-16 07:20:40]

djordje.pesic@imgtec.com changed reviewers:
+ paul.lind@imgtec.com

[Djordje.Pesic, 2015-11-16 07:21:10]

Description was changed from

==========
MIPS: Enable movt, movz, movn and movf instructions on mips32r1

BUG=
==========

to

==========
MIPS: Enable movt, movz, movn and movf instructions on mips32r1
==========

[paul.l..., 2015-11-16 07:35:47]

paul.lind@imgtec.com changed reviewers:
+ petar.jovanovic@imgtec.com

[paul.l..., 2015-11-16 07:35:48]

I believe that all these instruction are also supported on the pre-mips32 arch's
which we have under the mips_arch_variant of 'loongson'. Please double check,
and add that variant if appropriate. LGTM.

[petarj, 2015-11-16 15:10:39]

I am probably added as a reviewer by accident, but here are my 2 cents anyway.

You may want to change these checks into DCHECK(!IsMipsArchVariant(kMips32r6));
if the instructions are supported for kLoongson variant as well. Speaking of
which, not all FP registers are allowed for Loongson CPUs if it is in FR=0 mode,
yet I do not know if it is necessary to incorporate that in DCHECKs here.

Having said this, I find unclear what kLoongson really means in the context of
v8 today.
The comment in constants-mips.h says:

// The loongson flag refers to the LOONGSON architectures based on MIPS-III,
// which predates (and is a subset of) the mips32r2 and r1 architectures.

This would mean that we support older Loongson CPUs such as 2F which I believe
we do not anymore. Am I wrong? If I am correct that we support 3A and newer
cores only, than we are being too restrictive on code generation (e.g. we could
allow instructions introduced in mips32, such as movz, etc).

[paul.l..., 2015-11-16 15:25:50]

Djordje, please change to Petar suggested approach:
DCHECK(!IsMipsArchVariant(kMips32r6));

[paul.l..., 2015-11-17 15:18:44]

lgtm

[Djordje.Pesic, 2015-11-17 16:31:53]

The CQ bit was checked by djordje.pesic@imgtec.com

[commit-bot: I haz the power, 2015-11-17 16:31:55]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1448843002/20001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1448843002/20001

[commit-bot: I haz the power, 2015-11-17 16:56:20]

Committed patchset #2 (id:20001)

[commit-bot: I haz the power, 2015-11-17 16:56:54]

Patchset 2 (id:??) landed as
https://crrev.com/d40445884939341c33a78d64962686ddee2a733e
Cr-Commit-Position: refs/heads/master@{#32054}