Subzero: Do some cleanup on the regalloc code.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 275 matching lines @@
     RegExclude |= RegSet_FramePointer;
   llvm::SmallBitVector RegMask = getRegisterSet(RegInclude, RegExclude);
   bool Repeat = (Kind == RAK_Global && Ctx->getFlags().shouldRepeatRegAlloc());
   do {
     LinearScan.init(Kind);
     LinearScan.scan(RegMask, Ctx->getFlags().shouldRandomizeRegAlloc());
     if (!LinearScan.hasEvictions())
       Repeat = false;
     Kind = RAK_SecondChance;
   } while (Repeat);
+  // TODO(stichnot): Run the register allocator one more time to do stack slot
+  // coalescing.  The idea would be to initialize the Unhandled list with the
+  // set of Variables that have no register and a non-empty live range, and
+  // model an infinite number of registers.  Maybe use the register aliasing
+  // mechanism to get better packing of narrower slots.
 }
 
 void TargetLowering::markRedefinitions() {
   // Find (non-SSA) instructions where the Dest variable appears in some source
   // operand, and set the IsDestRedefined flag to keep liveness analysis
   // consistent.
   for (auto Inst = Context.getCur(), E = Context.getNext(); Inst != E; ++Inst) {
     if (Inst->isDeleted())
       continue;
     Variable *Dest = Inst->getDest();
@@ skipping 337 matching lines @@
   if (Target == Target_##X)                                                    \
     return TargetHeader##X::create(Ctx);
 #include "llvm/Config/SZTargets.def"
 
   llvm::report_fatal_error("Unsupported target header lowering");
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() = default;
 
 } // end of namespace Ice