Subzero: Do some cleanup on the regalloc code.

src/IceRegAlloc.cpp

 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 31 matching lines @@
     if (Item->getLiveRange().overlapsInst(Def->getNumber(), UseTrimmed))
       return true;
   }
   return false;
 }
 
 void dumpDisableOverlap(const Cfg *Func, const Variable *Var,
                         const char *Reason) {
   if (!BuildDefs::dump())
     return;
-  if (Func->isVerbose(IceV_LinearScan)) {
-    VariablesMetadata *VMetadata = Func->getVMetadata();
-    Ostream &Str = Func->getContext()->getStrDump();
-    Str << "Disabling Overlap due to " << Reason << " " << *Var
-        << " LIVE=" << Var->getLiveRange() << " Defs=";
-    if (const Inst *FirstDef = VMetadata->getFirstDefinition(Var))
-      Str << FirstDef->getNumber();
-    const InstDefList &Defs = VMetadata->getLatterDefinitions(Var);
-    for (size_t i = 0; i < Defs.size(); ++i) {
-      Str << "," << Defs[i]->getNumber();
-    }
-    Str << "\n";
+  if (!Func->isVerbose(IceV_LinearScan))
+    return;
+
+  VariablesMetadata *VMetadata = Func->getVMetadata();
+  Ostream &Str = Func->getContext()->getStrDump();
+  Str << "Disabling Overlap due to " << Reason << " " << *Var
+      << " LIVE=" << Var->getLiveRange() << " Defs=";
+  if (const Inst *FirstDef = VMetadata->getFirstDefinition(Var))
+    Str << FirstDef->getNumber();
+  const InstDefList &Defs = VMetadata->getLatterDefinitions(Var);
+  for (size_t i = 0; i < Defs.size(); ++i) {
+    Str << "," << Defs[i]->getNumber();
   }
+  Str << "\n";
 }
 
 void dumpLiveRange(const Variable *Var, const Cfg *Func) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   char buf[30];
   snprintf(buf, llvm::array_lengthof(buf), "%2d", Var->getRegNumTmp());
   Str << "R=" << buf << "  V=";
   Var->dump(Func);
@@ skipping 78 matching lines @@
         << ", variable " << Var->getName(Func) << "\n";
   }
   for (SizeT VarNum : UsesBeforeDefs) {
     Variable *Var = Vars[VarNum];
     Str << "LR use before def, instruction " << LREnd[VarNum] << ", variable "
         << Var->getName(Func) << "\n";
   }
   return false;
 }
 
-// Prepare for very simple register allocation of only infinite-weight
-// Variables while respecting pre-colored Variables. Some properties we take
-// advantage of:
+// Prepare for very simple register allocation of only infinite-weight Variables
+// while respecting pre-colored Variables. Some properties we take advantage of:
 //
 // * Live ranges of interest consist of a single segment.
 //
 // * Live ranges of interest never span a call instruction.
 //
 // * Phi instructions are not considered because either phis have already been
 //   lowered, or they don't contain any pre-colored or infinite-weight
 //   Variables.
 //
-// * We don't need to renumber instructions before computing live ranges
-//   because all the high-level ICE instructions are deleted prior to lowering,
-//   and the low-level instructions are added in monotonically increasing order.
+// * We don't need to renumber instructions before computing live ranges because
+//   all the high-level ICE instructions are deleted prior to lowering, and the
+//   low-level instructions are added in monotonically increasing order.
 //
 // * There are no opportunities for register preference or allowing overlap.
 //
 // Some properties we aren't (yet) taking advantage of:
 //
 // * Because live ranges are a single segment, the Inactive set will always be
 //   empty, and the live range trimming operation is unnecessary.
 //
-// * Calculating overlap of single-segment live ranges could be optimized a
-//   bit.
+// * Calculating overlap of single-segment live ranges could be optimized a bit.
 void LinearScan::initForInfOnly() {
   TimerMarker T(TimerStack::TT_initUnhandled, Func);
   FindPreference = false;
   FindOverlap = false;
   SizeT NumVars = 0;
   const VarList &Vars = Func->getVariables();
 
   // Iterate across all instructions and record the begin and end of the live
   // range for each variable that is pre-colored or infinite weight.
   CfgVector<InstNumberT> LRBegin(Vars.size(), Inst::NumberSentinel);
@@ skipping 145 matching lines @@
   std::sort(UnhandledPrecolored.rbegin(), UnhandledPrecolored.rend(),
             CompareRanges);
 
   Handled.reserve(Unhandled.size());
   Inactive.reserve(Unhandled.size());
   Active.reserve(Unhandled.size());
   Evicted.reserve(Unhandled.size());
 }
 
 // This is called when Cur must be allocated a register but no registers are
-// available across Cur's live range. To handle this, we find a register that
-// is not explicitly used during Cur's live range, spill that register to a
-// stack location right before Cur's live range begins, and fill (reload) the
-// register from the stack location right after Cur's live range ends.
+// available across Cur's live range. To handle this, we find a register that is
+// not explicitly used during Cur's live range, spill that register to a stack
+// location right before Cur's live range begins, and fill (reload) the register
+// from the stack location right after Cur's live range ends.
 void LinearScan::addSpillFill(IterationState &Iter) {
   // Identify the actual instructions that begin and end Iter.Cur's live range.
   // Iterate through Iter.Cur's node's instruction list until we find the actual
   // instructions with instruction numbers corresponding to Iter.Cur's recorded
   // live range endpoints.  This sounds inefficient but shouldn't be a problem
   // in practice because:
   // (1) This function is almost never called in practice.
   // (2) Since this register over-subscription problem happens only for
   //     phi-lowered instructions, the number of instructions in the node is
   //     proportional to the number of phi instructions in the original node,
@@ skipping 11 matching lines @@
   InstList::iterator SpillPoint = Insts.end();
   InstList::iterator FillPoint = Insts.end();
   // Stop searching after we have found both the SpillPoint and the FillPoint.
   for (auto I = Insts.begin(), E = Insts.end();
        I != E && (SpillPoint == E || FillPoint == E); ++I) {
     if (I->getNumber() == Start)
       SpillPoint = I;
     if (I->getNumber() == End)
       FillPoint = I;
     if (SpillPoint != E) {
-      // Remove from RegMask any physical registers referenced during Cur's
-      // live range. Start looking after SpillPoint gets set, i.e. once Cur's
-      // live range begins.
+      // Remove from RegMask any physical registers referenced during Cur's live
+      // range. Start looking after SpillPoint gets set, i.e. once Cur's live
+      // range begins.
       FOREACH_VAR_IN_INST(Var, *I) {
         if (!Var->hasRegTmp())
           continue;
         const llvm::SmallBitVector &Aliases = *RegAliases[Var->getRegNumTmp()];
         for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
              RegAlias = Aliases.find_next(RegAlias)) {
           Iter.RegMask[RegAlias] = false;
         }
       }
     }
   }
   assert(SpillPoint != Insts.end());
   assert(FillPoint != Insts.end());
   ++FillPoint;
   // TODO(stichnot): Randomize instead of find_first().
   int32_t RegNum = Iter.RegMask.find_first();
   assert(RegNum != -1);
   Iter.Cur->setRegNumTmp(RegNum);
   Variable *Preg = Target->getPhysicalRegister(RegNum, Iter.Cur->getType());
-  // TODO(stichnot): Add SpillLoc to VariablesMetadata tracking so that
-  // SpillLoc is correctly identified as !isMultiBlock(), reducing stack frame
-  // size.
+  // TODO(stichnot): Add SpillLoc to VariablesMetadata tracking so that SpillLoc
+  // is correctly identified as !isMultiBlock(), reducing stack frame size.
   Variable *SpillLoc = Func->makeVariable(Iter.Cur->getType());
   // Add "reg=FakeDef;spill=reg" before SpillPoint
   Target->lowerInst(Node, SpillPoint, InstFakeDef::create(Func, Preg));
   Target->lowerInst(Node, SpillPoint, InstAssign::create(Func, SpillLoc, Preg));
   // add "reg=spill;FakeUse(reg)" before FillPoint
   Target->lowerInst(Node, FillPoint, InstAssign::create(Func, Preg, SpillLoc));
   Target->lowerInst(Node, FillPoint, InstFakeUse::create(Func, Preg));
 }
 
 void LinearScan::handleActiveRangeExpiredOrInactive(const Variable *Cur) {
@@ skipping 45 matching lines @@
       for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
            RegAlias = Aliases.find_next(RegAlias)) {
         assert(RegUses[RegAlias] >= 0);
         ++RegUses[RegAlias];
       }
     }
   }
 }
 
 // Infer register preference and allowable overlap. Only form a preference when
-// the current Variable has an unambiguous "first" definition. The preference
-// is some source Variable of the defining instruction that either is assigned
-// a register that is currently free, or that is assigned a register that is
-// not free but overlap is allowed. Overlap is allowed when the Variable under
-// consideration is single-definition, and its definition is a simple
-// assignment - i.e., the register gets copied/aliased but is never modified.
-// Furthermore, overlap is only allowed when preferred Variable definition
-// instructions do not appear within the current Variable's live range.
+// the current Variable has an unambiguous "first" definition. The preference is
+// some source Variable of the defining instruction that either is assigned a
+// register that is currently free, or that is assigned a register that is not
+// free but overlap is allowed. Overlap is allowed when the Variable under
+// consideration is single-definition, and its definition is a simple assignment
+// - i.e., the register gets copied/aliased but is never modified.  Furthermore,
+// overlap is only allowed when preferred Variable definition instructions do
+// not appear within the current Variable's live range.
 void LinearScan::findRegisterPreference(IterationState &Iter) {
   Iter.Prefer = nullptr;
   Iter.PreferReg = Variable::NoRegister;
   Iter.AllowOverlap = false;
 
-  if (FindPreference) {
-    VariablesMetadata *VMetadata = Func->getVMetadata();
-    if (const Inst *DefInst =
-            VMetadata->getFirstDefinitionSingleBlock(Iter.Cur)) {
-      assert(DefInst->getDest() == Iter.Cur);
-      bool IsAssign = DefInst->isVarAssign();
-      bool IsSingleDef = !VMetadata->isMultiDef(Iter.Cur);
-      FOREACH_VAR_IN_INST(SrcVar, *DefInst) {
-        // Only consider source variables that have (so far) been assigned a
-        // register. That register must be one in the RegMask set, e.g. don't
-        // try to prefer the stack pointer as a result of the stacksave
-        // intrinsic.
-        if (SrcVar->hasRegTmp()) {
-          const llvm::SmallBitVector &Aliases =
-              *RegAliases[SrcVar->getRegNumTmp()];
-          const int32_t SrcReg = (Iter.RegMask & Aliases).find_first();
-          const bool IsAliasAvailable = (SrcReg != -1);
-          if (IsAliasAvailable) {
-            if (FindOverlap && !Iter.Free[SrcReg]) {
-              // Don't bother trying to enable AllowOverlap if the register is
-              // already free.
-              Iter.AllowOverlap = IsSingleDef && IsAssign &&
-                                  !overlapsDefs(Func, Iter.Cur, SrcVar);
-            }
-            if (Iter.AllowOverlap || Iter.Free[SrcReg]) {
-              Iter.Prefer = SrcVar;
-              Iter.PreferReg = SrcReg;
-              // Stop looking for a preference after the first valid preference
-              // is found.  One might think that we should look at all
-              // instruction variables to find the best <Prefer,AllowOverlap>
-              // combination, but note that AllowOverlap can only be true for a
-              // simple assignment statement which can have only one source
-              // operand, so it's not possible for AllowOverlap to be true
-              // beyond the first source operand.
-              FOREACH_VAR_IN_INST_BREAK;
-            }
-          }
-        }
-      }
-      if (Verbose && Iter.Prefer) {
-        Ostream &Str = Ctx->getStrDump();
-        Str << "Initial Iter.Prefer=";
-        Iter.Prefer->dump(Func);
-        Str << " R=" << Iter.PreferReg
-            << " LIVE=" << Iter.Prefer->getLiveRange()
-            << " Overlap=" << Iter.AllowOverlap << "\n";
-      }
+  if (!FindPreference)
+    return;
+
+  VariablesMetadata *VMetadata = Func->getVMetadata();
+  const Inst *DefInst = VMetadata->getFirstDefinitionSingleBlock(Iter.Cur);
+  if (DefInst == nullptr)
+    return;
+
+  assert(DefInst->getDest() == Iter.Cur);
+  const bool IsSingleDefAssign =
+      DefInst->isVarAssign() && !VMetadata->isMultiDef(Iter.Cur);
+  FOREACH_VAR_IN_INST(SrcVar, *DefInst) {
+    // Only consider source variables that have (so far) been assigned a
+    // register.
+    if (!SrcVar->hasRegTmp())
+      continue;
+
+    // That register must be one in the RegMask set, e.g. don't try to prefer
+    // the stack pointer as a result of the stacksave intrinsic.
+    const llvm::SmallBitVector &Aliases = *RegAliases[SrcVar->getRegNumTmp()];
+    const int32_t SrcReg = (Iter.RegMask & Aliases).find_first();
+    if (SrcReg == -1)
+      continue;
+
+    if (FindOverlap && IsSingleDefAssign && !Iter.Free[SrcReg]) {
+      // Don't bother trying to enable AllowOverlap if the register is already
+      // free (hence the test on Iter.Free[SrcReg]).
+      Iter.AllowOverlap = !overlapsDefs(Func, Iter.Cur, SrcVar);
     }
+    if (Iter.AllowOverlap || Iter.Free[SrcReg]) {
+      Iter.Prefer = SrcVar;
+      Iter.PreferReg = SrcReg;
+      // Stop looking for a preference after the first valid preference is
+      // found.  One might think that we should look at all instruction
+      // variables to find the best <Prefer,AllowOverlap> combination, but note
+      // that AllowOverlap can only be true for a simple assignment statement
+      // which can have only one source operand, so it's not possible for
+      // AllowOverlap to be true beyond the first source operand.
+      FOREACH_VAR_IN_INST_BREAK;
+    }
+  }
+  if (BuildDefs::dump() && Verbose && Iter.Prefer) {
+    Ostream &Str = Ctx->getStrDump();
+    Str << "Initial Iter.Prefer=";
+    Iter.Prefer->dump(Func);
+    Str << " R=" << Iter.PreferReg << " LIVE=" << Iter.Prefer->getLiveRange()
+        << " Overlap=" << Iter.AllowOverlap << "\n";
   }
 }
 
 // Remove registers from the Free[] list where an Inactive range overlaps with
 // the current range.
 void LinearScan::filterFreeWithInactiveRanges(IterationState &Iter) {
   for (const Variable *Item : Inactive) {
     if (!Item->rangeOverlaps(Iter.Cur))
       continue;
     const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
     // TODO(stichnot): Do this with bitvector ops, not a loop, for efficiency.
     for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
          RegAlias = Aliases.find_next(RegAlias)) {
       // Don't assert(Free[RegNum]) because in theory (though probably never in
       // practice) there could be two inactive variables that were marked with
       // AllowOverlap.
       Iter.Free[RegAlias] = false;
       // Disable AllowOverlap if an Inactive variable, which is not Prefer,
-      // shares Prefer's register, and has a definition within Cur's live
-      // range.
+      // shares Prefer's register, and has a definition within Cur's live range.
       if (Iter.AllowOverlap && Item != Iter.Prefer &&
           RegAlias == Iter.PreferReg && overlapsDefs(Func, Iter.Cur, Item)) {
         Iter.AllowOverlap = false;
         dumpDisableOverlap(Func, Item, "Inactive");
       }
     }
   }
 }
 
 // Remove registers from the Free[] list where an Unhandled pre-colored range
 // overlaps with the current range, and set those registers to infinite weight
-// so that they aren't candidates for eviction. Cur->rangeEndsBefore(Item) is
-// an early exit check that turns a guaranteed O(N^2) algorithm into expected
+// so that they aren't candidates for eviction. Cur->rangeEndsBefore(Item) is an
+// early exit check that turns a guaranteed O(N^2) algorithm into expected
 // linear complexity.
 void LinearScan::filterFreeWithPrecoloredRanges(IterationState &Iter) {
   for (Variable *Item : reverse_range(UnhandledPrecolored)) {
     assert(Item->hasReg());
     if (Iter.Cur->rangeEndsBefore(Item))
       break;
-    if (Item->rangeOverlaps(Iter.Cur)) {
-      const llvm::SmallBitVector &Aliases =
-          *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp()
-      for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
-           RegAlias = Aliases.find_next(RegAlias)) {
-        Iter.Weights[RegAlias].setWeight(RegWeight::Inf);
-        Iter.Free[RegAlias] = false;
-        Iter.PrecoloredUnhandledMask[RegAlias] = true;
-        // Disable Iter.AllowOverlap if the preferred register is one of these
-        // pre-colored unhandled overlapping ranges.
-        if (Iter.AllowOverlap && RegAlias == Iter.PreferReg) {
-          Iter.AllowOverlap = false;
-          dumpDisableOverlap(Func, Item, "PrecoloredUnhandled");
-        }
+    if (!Item->rangeOverlaps(Iter.Cur))
+      continue;
+    const llvm::SmallBitVector &Aliases =
+        *RegAliases[Item->getRegNum()]; // Note: not getRegNumTmp()
+    for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
+         RegAlias = Aliases.find_next(RegAlias)) {
+      Iter.Weights[RegAlias].setWeight(RegWeight::Inf);
+      Iter.Free[RegAlias] = false;
+      Iter.PrecoloredUnhandledMask[RegAlias] = true;
+      // Disable Iter.AllowOverlap if the preferred register is one of these
+      // pre-colored unhandled overlapping ranges.
+      if (Iter.AllowOverlap && RegAlias == Iter.PreferReg) {
+        Iter.AllowOverlap = false;
+        dumpDisableOverlap(Func, Item, "PrecoloredUnhandled");
       }
     }
   }
 }
 
 void LinearScan::allocatePrecoloredRegister(Variable *Cur) {
   int32_t RegNum = Cur->getRegNum();
   // RegNumTmp should have already been set above.
   assert(Cur->getRegNumTmp() == RegNum);
   dumpLiveRangeTrace("Precoloring  ", Cur);
@@ skipping 55 matching lines @@
       continue;
     assert(Item->hasRegTmp());
     const llvm::SmallBitVector &Aliases = *RegAliases[Item->getRegNumTmp()];
     RegWeight W = Item->getWeight(Func);
     for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
          RegAlias = Aliases.find_next(RegAlias)) {
       Iter.Weights[RegAlias].addWeight(W);
     }
   }
 
-  // All the weights are now calculated. Find the register with smallest
-  // weight.
+  // All the weights are now calculated. Find the register with smallest weight.
   int32_t MinWeightIndex = Iter.RegMask.find_first();
   // MinWeightIndex must be valid because of the initial RegMask.any() test.
   assert(MinWeightIndex >= 0);
   for (SizeT i = MinWeightIndex + 1; i < Iter.Weights.size(); ++i) {
     if (Iter.RegMask[i] && Iter.Weights[i] < Iter.Weights[MinWeightIndex])
       MinWeightIndex = i;
   }
 
   if (Iter.Cur->getWeight(Func) <= Iter.Weights[MinWeightIndex]) {
     // Cur doesn't have priority over any other live ranges, so don't allocate
@@ skipping 27 matching lines @@
         Evicted.push_back(Item);
       }
     }
     // Do the same for Inactive.
     for (SizeT I = Inactive.size(); I > 0; --I) {
       const SizeT Index = I - 1;
       Variable *Item = Inactive[Index];
       // Note: The Item->rangeOverlaps(Cur) clause is not part of the
       // description of AssignMemLoc() in the original paper. But there doesn't
       // seem to be any need to evict an inactive live range that doesn't
-      // overlap with the live range currently being considered. It's
-      // especially bad if we would end up evicting an infinite-weight but
-      // currently-inactive live range. The most common situation for this
-      // would be a scratch register kill set for call instructions.
+      // overlap with the live range currently being considered. It's especially
+      // bad if we would end up evicting an infinite-weight but
+      // currently-inactive live range. The most common situation for this would
+      // be a scratch register kill set for call instructions.
       if (Aliases[Item->getRegNumTmp()] && Item->rangeOverlaps(Iter.Cur)) {
         dumpLiveRangeTrace("Evicting I   ", Item);
         Item->setRegNumTmp(Variable::NoRegister);
         moveItem(Inactive, Index, Handled);
         Evicted.push_back(Item);
       }
     }
     // Assign the register to Cur.
     Iter.Cur->setRegNumTmp(MinWeightIndex);
     for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0;
@@ skipping 25 matching lines @@
 
   // Finish up by setting RegNum = RegNumTmp (or a random permutation thereof)
   // for each Variable.
   for (Variable *Item : Handled) {
     int32_t RegNum = Item->getRegNumTmp();
     int32_t AssignedRegNum = RegNum;
 
     if (Randomized && Item->hasRegTmp() && !Item->hasReg()) {
       AssignedRegNum = Permutation[RegNum];
     }
-    if (Verbose) {
+    if (BuildDefs::dump() && Verbose) {
       Ostream &Str = Ctx->getStrDump();
       if (!Item->hasRegTmp()) {
         Str << "Not assigning ";
         Item->dump(Func);
         Str << "\n";
       } else {
         Str << (AssignedRegNum == Item->getRegNum() ? "Reassigning "
                                                     : "Assigning ")
             << Target->getRegName(AssignedRegNum, IceType_i32) << "(r"
             << AssignedRegNum << ") to ";
         Item->dump(Func);
         Str << "\n";
       }
     }
     Item->setRegNum(AssignedRegNum);
   }
 }
 
 // Implements the linear-scan algorithm. Based on "Linear Scan Register
 // Allocation in the Context of SSA Form and Register Constraints" by Hanspeter
 // Mössenböck and Michael Pfeiffer,
 // ftp://ftp.ssw.uni-linz.ac.at/pub/Papers/Moe02.PDF. This implementation is
-// modified to take affinity into account and allow two interfering variables
-// to share the same register in certain cases.
+// modified to take affinity into account and allow two interfering variables to
+// share the same register in certain cases.
 //
 // Requires running Cfg::liveness(Liveness_Intervals) in preparation. Results
 // are assigned to Variable::RegNum for each Variable.
 void LinearScan::scan(const llvm::SmallBitVector &RegMaskFull,
                       bool Randomized) {
   TimerMarker T(TimerStack::TT_linearScan, Func);
   assert(RegMaskFull.any()); // Sanity check
   if (Verbose)
     Ctx->lockStr();
   Func->resetCurrentNode();
   const size_t NumRegisters = RegMaskFull.size();
   llvm::SmallBitVector PreDefinedRegisters(NumRegisters);
   if (Randomized) {
     for (Variable *Var : UnhandledPrecolored) {
       PreDefinedRegisters[Var->getRegNum()] = true;
     }
   }
 
   // Build a LiveRange representing the Kills list.
   LiveRange KillsRange(Kills);
   KillsRange.untrim();
 
-  // Reset the register use count
+  // Reset the register use count.
   RegUses.resize(NumRegisters);
   std::fill(RegUses.begin(), RegUses.end(), 0);
 
-  // Unhandled is already set to all ranges in increasing order of start
-  // points.
+  // Unhandled is already set to all ranges in increasing order of start points.
   assert(Active.empty());
   assert(Inactive.empty());
   assert(Handled.empty());
   const TargetLowering::RegSetMask RegsInclude =
       TargetLowering::RegSet_CallerSave;
   const TargetLowering::RegSetMask RegsExclude = TargetLowering::RegSet_None;
   const llvm::SmallBitVector KillsMask =
       Target->getRegisterSet(RegsInclude, RegsExclude);
 
-  // Allocate memory once outside the loop
+  // Allocate memory once outside the loop.
   IterationState Iter;
   Iter.Weights.reserve(NumRegisters);
   Iter.PrecoloredUnhandledMask.reserve(NumRegisters);
 
   while (!Unhandled.empty()) {
     Iter.Cur = Unhandled.back();
     Unhandled.pop_back();
     dumpLiveRangeTrace("\nConsidering  ", Iter.Cur);
     Iter.RegMask = RegMaskFull & Target->getRegistersForVariable(Iter.Cur);
     KillsRange.trim(Iter.Cur->getLiveRange().getStart());
@@ skipping 49 matching lines @@
       Iter.Free.reset(KillsMask);
       for (int i = KillsMask.find_first(); i != -1;
            i = KillsMask.find_next(i)) {
         Iter.Weights[i].setWeight(RegWeight::Inf);
         if (Iter.PreferReg == i)
           Iter.AllowOverlap = false;
       }
     }
 
     // Print info about physical register availability.
-    if (Verbose) {
+    if (BuildDefs::dump() && Verbose) {
       Ostream &Str = Ctx->getStrDump();
       for (SizeT i = 0; i < Iter.RegMask.size(); ++i) {
         if (Iter.RegMask[i]) {
           Str << Target->getRegName(i, IceType_i32) << "(U=" << RegUses[i]
               << ",F=" << Iter.Free[i]
               << ",P=" << Iter.PrecoloredUnhandledMask[i] << ") ";
         }
       }
       Str << "\n";
     }
 
     if (Iter.Prefer && (Iter.AllowOverlap || Iter.Free[Iter.PreferReg])) {
-      // First choice: a preferred register that is either free or is allowed
-      // to overlap with its linked variable.
+      // First choice: a preferred register that is either free or is allowed to
+      // overlap with its linked variable.
       allocatePreferredRegister(Iter);
     } else if (Iter.Free.any()) {
       // Second choice: any free register.
       allocateFreeRegister(Iter);
     } else {
-      // Fallback: there are no free registers, so we look for the
-      // lowest-weight register and see if Cur has higher weight.
+      // Fallback: there are no free registers, so we look for the lowest-weight
+      // register and see if Cur has higher weight.
       handleNoFreeRegisters(Iter);
     }
     dump(Func);
   }
 
   // Move anything Active or Inactive to Handled for easier handling.
   Handled.insert(Handled.end(), Active.begin(), Active.end());
   Active.clear();
   Handled.insert(Handled.end(), Inactive.begin(), Inactive.end());
   Inactive.clear();
   dump(Func);
 
   assignFinalRegisters(RegMaskFull, PreDefinedRegisters, Randomized);
 
-  // TODO: Consider running register allocation one more time, with infinite
-  // registers, for two reasons. First, evicted live ranges get a second chance
-  // for a register. Second, it allows coalescing of stack slots. If there is
-  // no time budget for the second register allocation run, each unallocated
-  // variable just gets its own slot.
-  //
-  // Another idea for coalescing stack slots is to initialize the Unhandled
-  // list with just the unallocated variables, saving time but not offering
-  // second-chance opportunities.
-
   if (Verbose)
     Ctx->unlockStr();
 }
 
 // ======================== Dump routines ======================== //
 
 void LinearScan::dumpLiveRangeTrace(const char *Label, const Variable *Item) {
   if (!BuildDefs::dump())
     return;
 
   if (Verbose) {
     Ostream &Str = Ctx->getStrDump();
     Str << Label;
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 void LinearScan::dump(Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
-  if (!Func->isVerbose(IceV_LinearScan))
+  if (!Verbose)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Func->resetCurrentNode();
   Str << "**** Current regalloc state:\n";
   Str << "++++++ Handled:\n";
   for (const Variable *Item : Handled) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Unhandled:\n";
   for (const Variable *Item : reverse_range(Unhandled)) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Active:\n";
   for (const Variable *Item : Active) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
   Str << "++++++ Inactive:\n";
   for (const Variable *Item : Inactive) {
     dumpLiveRange(Item, Func);
     Str << "\n";
   }
 }
 
 } // end of namespace Ice