MIPS: Implementation of Float64RoundUp and Float64RoundTiesEven

MIPS: Implementation of Float64RoundUp and Float64RoundTiesEven

Port 1389b9f53c90dca1ff123cf3a1e90c607dadfc90
Port dffecf31fc069c9522bcb09df7c063a9710f6470

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=

Committed: https://crrev.com/5e9c4716d158aced80fa5c7306468909a621082a
Cr-Commit-Position: refs/heads/master@{#32108}

[ivica.bogosavljevic, 2015-11-18 08:22:01]

Description was changed from

==========
[MIPS] Implementation of Float64RoundUp and Float64RoundTiesEven

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

to

==========
[MIPS] Implementation of Float64RoundUp and Float64RoundTiesEven

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

[ivica.bogosavljevic, 2015-11-18 08:22:01]

ivica.bogosavljevic@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com, balazs.kilvady@imgtec.com, paul.lind@imgtec.com

[paul.l..., 2015-11-19 00:09:26]

paul.lind@imgtec.com changed reviewers:
+ ahaas@chromium.org

[paul.l..., 2015-11-19 00:09:26]

nits: please edit title to "MIPS: Implementation of ...". No brackets on
per-arch ports.

And 1 line below title, before message body, add:
Port 1389b9f53c90dca1ff123cf3a1e90c607dadfc90
Port dffecf31fc069c9522bcb09df7c063a9710f6470

Then LGTM!

Andreas, I was mistaken about the rounding instructions that your port used, so
Ivica has just included the work in mips32 that I asked you to remove. Sorry
about that!. He did add some protection for using those instructions in the
wrong mode -- see commit msg. But that wasn't the case in your CLs.

[ivica.bogosavljevic, 2015-11-19 08:47:07]

Description was changed from

==========
[MIPS] Implementation of Float64RoundUp and Float64RoundTiesEven

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

to

==========
MIPS Implementation of Float64RoundUp and Float64RoundTiesEven

Port 1389b9f53c90dca1ff123cf3a1e90c607dadfc90
Port dffecf31fc069c9522bcb09df7c063a9710f6470

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

[ivica.bogosavljevic, 2015-11-19 08:47:30]

Description was changed from

==========
MIPS Implementation of Float64RoundUp and Float64RoundTiesEven

Port 1389b9f53c90dca1ff123cf3a1e90c607dadfc90
Port dffecf31fc069c9522bcb09df7c063a9710f6470

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

to

==========
MIPS: Implementation of Float64RoundUp and Float64RoundTiesEven

Port 1389b9f53c90dca1ff123cf3a1e90c607dadfc90
Port dffecf31fc069c9522bcb09df7c063a9710f6470

Implementation of two optional turbofan operators Float64RoundUp and
Float64RoundTiesEven on MIPS32. On MIPS32R2 with FP64 and MIPS32R6 with FP64
we can support these two operators directly using MIPS instructions. This
code implements these two operators. Also, added some DCHECKs for instructions
which are supported on MIPS32R2 with FP64 and MIPS32R6 with FP64 to detect
wrong usage on unsupported architectures.

BUG=
==========

[ivica.bogosavljevic, 2015-11-19 08:51:41]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[commit-bot: I haz the power, 2015-11-19 08:51:46]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1448383002/1
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1448383002/1

[commit-bot: I haz the power, 2015-11-19 08:54:07]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2015-11-19 08:54:08]

Try jobs failed on following builders:
  v8_presubmit on tryserver.v8 (JOB_FAILED,
http://build.chromium.org/p/tryserver.v8/builders/v8_presubmit/builds/7880)

[ivica.bogosavljevic, 2015-11-19 10:15:25]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2015-11-19 10:15:29]

Dry run: CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1448383002/20001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1448383002/20001

[commit-bot: I haz the power, 2015-11-19 10:35:57]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2015-11-19 10:35:58]

Dry run: This issue passed the CQ dry run.

[ivica.bogosavljevic, 2015-11-19 10:38:57]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[ivica.bogosavljevic, 2015-11-19 10:38:58]

The patchset sent to the CQ was uploaded after l-g-t-m from paul.lind@imgtec.com
Link to the patchset: https://codereview.chromium.org/1448383002/#ps20001
(title: "Fixing CLINT warning on function size")

[commit-bot: I haz the power, 2015-11-19 10:39:03]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1448383002/20001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1448383002/20001

[commit-bot: I haz the power, 2015-11-19 10:40:20]

Committed patchset #2 (id:20001)

[commit-bot: I haz the power, 2015-11-19 10:40:36]

Patchset 2 (id:??) landed as
https://crrev.com/5e9c4716d158aced80fa5c7306468909a621082a
Cr-Commit-Position: refs/heads/master@{#32108}

[Igor Sheludko, 2015-11-19 14:29:04]

On 2015/11/19 at 10:40:36, commit-bot wrote:
> Patchset 2 (id:??) landed as
https://crrev.com/5e9c4716d158aced80fa5c7306468909a621082a
> Cr-Commit-Position: refs/heads/master@{#32108}

This CL breaks several cctests in [opt]debug mode. For example:
cctest/test-assembler-mips/CVT