| Index: base/cpu_unittest.cc
|
| diff --git a/base/cpu_unittest.cc b/base/cpu_unittest.cc
|
| index 18bf959a55edaac568e4feebd8bf018321657034..d3d52f2c02c2e1ffc793e3026c745df46367224a 100644
|
| --- a/base/cpu_unittest.cc
|
| +++ b/base/cpu_unittest.cc
|
| @@ -17,43 +17,7 @@ TEST(CPU, RunExtendedInstructions) {
|
| // Retrieve the CPU information.
|
| base::CPU cpu;
|
|
|
| -// TODO(jschuh): crbug.com/168866 Find a way to enable this on Win64.
|
| -#if defined(OS_WIN) && !defined(_M_X64)
|
| - ASSERT_TRUE(cpu.has_mmx());
|
| -
|
| - // Execute an MMX instruction.
|
| - __asm emms;
|
| -
|
| - if (cpu.has_sse()) {
|
| - // Execute an SSE instruction.
|
| - __asm xorps xmm0, xmm0;
|
| - }
|
| -
|
| - if (cpu.has_sse2()) {
|
| - // Execute an SSE 2 instruction.
|
| - __asm psrldq xmm0, 0;
|
| - }
|
| -
|
| - if (cpu.has_sse3()) {
|
| - // Execute an SSE 3 instruction.
|
| - __asm addsubpd xmm0, xmm0;
|
| - }
|
| -
|
| - if (cpu.has_ssse3()) {
|
| - // Execute a Supplimental SSE 3 instruction.
|
| - __asm psignb xmm0, xmm0;
|
| - }
|
| -
|
| - if (cpu.has_sse41()) {
|
| - // Execute an SSE 4.1 instruction.
|
| - __asm pmuldq xmm0, xmm0;
|
| - }
|
| -
|
| - if (cpu.has_sse42()) {
|
| - // Execute an SSE 4.2 instruction.
|
| - __asm crc32 eax, eax;
|
| - }
|
| -#elif defined(OS_POSIX) && defined(__x86_64__)
|
| +#if defined(OS_POSIX) && defined(__x86_64__)
|
| ASSERT_TRUE(cpu.has_mmx());
|
|
|
| // Execute an MMX instruction.
|
|
|