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1 // Copyright (c) 2012 The Chromium Authors. All rights reserved. | 1 // Copyright (c) 2012 The Chromium Authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "base/cpu.h" | 5 #include "base/cpu.h" |
6 #include "build/build_config.h" | 6 #include "build/build_config.h" |
7 | 7 |
8 #include "testing/gtest/include/gtest/gtest.h" | 8 #include "testing/gtest/include/gtest/gtest.h" |
9 | 9 |
10 // Tests whether we can run extended instructions represented by the CPU | 10 // Tests whether we can run extended instructions represented by the CPU |
11 // information. This test actually executes some extended instructions (such as | 11 // information. This test actually executes some extended instructions (such as |
12 // MMX, SSE, etc.) supported by the CPU and sees we can run them without | 12 // MMX, SSE, etc.) supported by the CPU and sees we can run them without |
13 // "undefined instruction" exceptions. That is, this test succeeds when this | 13 // "undefined instruction" exceptions. That is, this test succeeds when this |
14 // test finishes without a crash. | 14 // test finishes without a crash. |
15 TEST(CPU, RunExtendedInstructions) { | 15 TEST(CPU, RunExtendedInstructions) { |
16 #if defined(ARCH_CPU_X86_FAMILY) | 16 #if defined(ARCH_CPU_X86_FAMILY) |
17 // Retrieve the CPU information. | 17 // Retrieve the CPU information. |
18 base::CPU cpu; | 18 base::CPU cpu; |
19 | 19 |
20 // TODO(jschuh): crbug.com/168866 Find a way to enable this on Win64. | 20 #if defined(OS_POSIX) && defined(__x86_64__) |
21 #if defined(OS_WIN) && !defined(_M_X64) | |
22 ASSERT_TRUE(cpu.has_mmx()); | 21 ASSERT_TRUE(cpu.has_mmx()); |
23 | 22 |
24 // Execute an MMX instruction. | 23 // Execute an MMX instruction. |
25 __asm emms; | |
26 | |
27 if (cpu.has_sse()) { | |
28 // Execute an SSE instruction. | |
29 __asm xorps xmm0, xmm0; | |
30 } | |
31 | |
32 if (cpu.has_sse2()) { | |
33 // Execute an SSE 2 instruction. | |
34 __asm psrldq xmm0, 0; | |
35 } | |
36 | |
37 if (cpu.has_sse3()) { | |
38 // Execute an SSE 3 instruction. | |
39 __asm addsubpd xmm0, xmm0; | |
40 } | |
41 | |
42 if (cpu.has_ssse3()) { | |
43 // Execute a Supplimental SSE 3 instruction. | |
44 __asm psignb xmm0, xmm0; | |
45 } | |
46 | |
47 if (cpu.has_sse41()) { | |
48 // Execute an SSE 4.1 instruction. | |
49 __asm pmuldq xmm0, xmm0; | |
50 } | |
51 | |
52 if (cpu.has_sse42()) { | |
53 // Execute an SSE 4.2 instruction. | |
54 __asm crc32 eax, eax; | |
55 } | |
56 #elif defined(OS_POSIX) && defined(__x86_64__) | |
57 ASSERT_TRUE(cpu.has_mmx()); | |
58 | |
59 // Execute an MMX instruction. | |
60 __asm__ __volatile__("emms\n" : : : "mm0"); | 24 __asm__ __volatile__("emms\n" : : : "mm0"); |
61 | 25 |
62 if (cpu.has_sse()) { | 26 if (cpu.has_sse()) { |
63 // Execute an SSE instruction. | 27 // Execute an SSE instruction. |
64 __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0"); | 28 __asm__ __volatile__("xorps %%xmm0, %%xmm0\n" : : : "xmm0"); |
65 } | 29 } |
66 | 30 |
67 if (cpu.has_sse2()) { | 31 if (cpu.has_sse2()) { |
68 // Execute an SSE 2 instruction. | 32 // Execute an SSE 2 instruction. |
69 __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0"); | 33 __asm__ __volatile__("psrldq $0, %%xmm0\n" : : : "xmm0"); |
(...skipping 14 matching lines...) Expand all Loading... |
84 __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0"); | 48 __asm__ __volatile__("pmuldq %%xmm0, %%xmm0\n" : : : "xmm0"); |
85 } | 49 } |
86 | 50 |
87 if (cpu.has_sse42()) { | 51 if (cpu.has_sse42()) { |
88 // Execute an SSE 4.2 instruction. | 52 // Execute an SSE 4.2 instruction. |
89 __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax"); | 53 __asm__ __volatile__("crc32 %%eax, %%eax\n" : : : "eax"); |
90 } | 54 } |
91 #endif | 55 #endif |
92 #endif | 56 #endif |
93 } | 57 } |
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