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Side by Side Diff: src/ppc/constants-ppc.h

Issue 1440733002: PPC64: Implemented the RoundUint64ToFloat64 TurboFan operator. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_PPC_CONSTANTS_PPC_H_ 5 #ifndef V8_PPC_CONSTANTS_PPC_H_
6 #define V8_PPC_CONSTANTS_PPC_H_ 6 #define V8_PPC_CONSTANTS_PPC_H_
7 7
8 #include <stdint.h> 8 #include <stdint.h>
9 9
10 #include "src/base/logging.h" 10 #include "src/base/logging.h"
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285 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate 285 MTFSFI = 134 << 1, // Move to FPSCR Field Immediate
286 FABS = 264 << 1, // Floating Absolute Value 286 FABS = 264 << 1, // Floating Absolute Value
287 FRIN = 392 << 1, // Floating Round to Integer Nearest 287 FRIN = 392 << 1, // Floating Round to Integer Nearest
288 FRIZ = 424 << 1, // Floating Round to Integer Toward Zero 288 FRIZ = 424 << 1, // Floating Round to Integer Toward Zero
289 FRIP = 456 << 1, // Floating Round to Integer Plus 289 FRIP = 456 << 1, // Floating Round to Integer Plus
290 FRIM = 488 << 1, // Floating Round to Integer Minus 290 FRIM = 488 << 1, // Floating Round to Integer Minus
291 MFFS = 583 << 1, // move from FPSCR x-form 291 MFFS = 583 << 1, // move from FPSCR x-form
292 MTFSF = 711 << 1, // move to FPSCR fields XFL-form 292 MTFSF = 711 << 1, // move to FPSCR fields XFL-form
293 FCFID = 846 << 1, // Floating convert from integer doubleword 293 FCFID = 846 << 1, // Floating convert from integer doubleword
294 FCTID = 814 << 1, // Floating convert from integer doubleword 294 FCTID = 814 << 1, // Floating convert from integer doubleword
295 FCTIDZ = 815 << 1 // Floating convert from integer doubleword 295 FCTIDZ = 815 << 1, // Floating convert from integer doubleword
296 FCFIDU = 974 << 1 // Floating convert from integer doubleword unsigned
296 }; 297 };
297 298
298 enum OpcodeExt5 { 299 enum OpcodeExt5 {
299 // Bits 4-2 300 // Bits 4-2
300 RLDICL = 0 << 1, // Rotate Left Double Word Immediate then Clear Left 301 RLDICL = 0 << 1, // Rotate Left Double Word Immediate then Clear Left
301 RLDICR = 2 << 1, // Rotate Left Double Word Immediate then Clear Right 302 RLDICR = 2 << 1, // Rotate Left Double Word Immediate then Clear Right
302 RLDIC = 4 << 1, // Rotate Left Double Word Immediate then Clear 303 RLDIC = 4 << 1, // Rotate Left Double Word Immediate then Clear
303 RLDIMI = 6 << 1, // Rotate Left Double Word Immediate then Mask Insert 304 RLDIMI = 6 << 1, // Rotate Left Double Word Immediate then Mask Insert
304 // Bits 4-1 305 // Bits 4-1
305 RLDCL = 8 << 1, // Rotate Left Double Word then Clear Left 306 RLDCL = 8 << 1, // Rotate Left Double Word then Clear Left
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578 // Lookup the register number for the name provided. 579 // Lookup the register number for the name provided.
579 static int Number(const char* name); 580 static int Number(const char* name);
580 581
581 private: 582 private:
582 static const char* names_[kNumDoubleRegisters]; 583 static const char* names_[kNumDoubleRegisters];
583 }; 584 };
584 } // namespace internal 585 } // namespace internal
585 } // namespace v8 586 } // namespace v8
586 587
587 #endif // V8_PPC_CONSTANTS_PPC_H_ 588 #endif // V8_PPC_CONSTANTS_PPC_H_
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