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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1440293002: [turbofan] Added the optional Float64RoundTiesEven operator to turbofan. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@f64roundup
Patch Set: Disabled F64RoundTiesEven on mips32 Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 51 matching lines...) Expand 10 before | Expand all | Expand 10 after
62 V(Mips64MulD) \ 62 V(Mips64MulD) \
63 V(Mips64DivD) \ 63 V(Mips64DivD) \
64 V(Mips64ModD) \ 64 V(Mips64ModD) \
65 V(Mips64AbsD) \ 65 V(Mips64AbsD) \
66 V(Mips64SqrtD) \ 66 V(Mips64SqrtD) \
67 V(Mips64MaxD) \ 67 V(Mips64MaxD) \
68 V(Mips64MinD) \ 68 V(Mips64MinD) \
69 V(Mips64Float64RoundDown) \ 69 V(Mips64Float64RoundDown) \
70 V(Mips64Float64RoundTruncate) \ 70 V(Mips64Float64RoundTruncate) \
71 V(Mips64Float64RoundUp) \ 71 V(Mips64Float64RoundUp) \
72 V(Mips64Float64RoundTiesEven) \
72 V(Mips64CvtSD) \ 73 V(Mips64CvtSD) \
73 V(Mips64CvtDS) \ 74 V(Mips64CvtDS) \
74 V(Mips64TruncWD) \ 75 V(Mips64TruncWD) \
75 V(Mips64TruncUwD) \ 76 V(Mips64TruncUwD) \
76 V(Mips64CvtDW) \ 77 V(Mips64CvtDW) \
77 V(Mips64CvtSL) \ 78 V(Mips64CvtSL) \
78 V(Mips64CvtDL) \ 79 V(Mips64CvtDL) \
79 V(Mips64CvtDUw) \ 80 V(Mips64CvtDUw) \
80 V(Mips64CvtDUl) \ 81 V(Mips64CvtDUl) \
81 V(Mips64Lb) \ 82 V(Mips64Lb) \
(...skipping 42 matching lines...) Expand 10 before | Expand all | Expand 10 after
124 #define TARGET_ADDRESSING_MODE_LIST(V) \ 125 #define TARGET_ADDRESSING_MODE_LIST(V) \
125 V(MRI) /* [%r0 + K] */ \ 126 V(MRI) /* [%r0 + K] */ \
126 V(MRR) /* [%r0 + %r1] */ 127 V(MRR) /* [%r0 + %r1] */
127 128
128 129
129 } // namespace compiler 130 } // namespace compiler
130 } // namespace internal 131 } // namespace internal
131 } // namespace v8 132 } // namespace v8
132 133
133 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 134 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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