Subzero: Add "--verbose=status" option.

src/IceInstX86BaseImpl.h

 //===- subzero/src/IceInstX86BaseImpl.h - Generic X86 instructions -*- C++ -*=//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1219 matching lines @@
   const Variable *Dest = Inst->getDest();
   const Operand *Src = Inst->getSrc(1);
   emitIASRegOpTyXMM<Machine>(Func, Dest->getType(), Dest, Src, Emitter);
 }
 
 template <class Machine>
 void InstX86Blendvps<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   emitVariableBlendInst<Machine>(this->Opcode, this, Func);
 }
 
 template <class Machine>
 void InstX86Blendvps<Machine>::emitIAS(const Cfg *Func) const {
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::blendvps,
                  &InstX86Base<Machine>::Traits::Assembler::blendvps};
   emitIASVariableBlendInst<Machine>(this, Func, Emitter);
 }
 
 template <class Machine>
 void InstX86Pblendvb<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   emitVariableBlendInst<Machine>(this->Opcode, this, Func);
 }
 
 template <class Machine>
 void InstX86Pblendvb<Machine>::emitIAS(const Cfg *Func) const {
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   static const typename InstX86Base<Machine>::Traits::Assembler::XmmEmitterRegOp
       Emitter = {&InstX86Base<Machine>::Traits::Assembler::pblendvb,
                  &InstX86Base<Machine>::Traits::Assembler::pblendvb};
   emitIASVariableBlendInst<Machine>(this, Func, Emitter);
 }
 
 template <class Machine>
@@ skipping 87 matching lines @@
       typename InstX86Base<Machine>::Traits::RegisterSet::GPRRegister,
       InstX86Base<Machine>::Traits::getEncodedGPR,
       InstX86Base<Machine>::Traits::getEncodedGPR>(
       Func, Ty, Dest, this->getSrc(0), this->getSrc(1), Emitter);
 }
 
 template <class Machine>
 void InstX86Insertps<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
              ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   const Variable *Dest = this->getDest();
   assert(Dest == this->getSrc(0));
   Type Ty = Dest->getType();
   static const typename InstX86Base<Machine>::Traits::Assembler::
       template ThreeOpImmEmitter<
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister,
           typename InstX86Base<Machine>::Traits::RegisterSet::XmmRegister>
@@ skipping 912 matching lines @@
                 ? this->getWidthString(DestTy)
                 : InstX86Base<Machine>::Traits::TypeAttributes[DestTy]
                       .SdSsString) << "\t";
   }
   // For an integer truncation operation, src is wider than dest. In this case,
   // we use a mov instruction whose data width matches the narrower dest.
   // TODO: This assert disallows usages such as copying a floating
   // point value between a vector and a scalar (which movss is used for). Clean
   // this up.
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(Target->typeWidthInBytesOnStack(DestTy) ==
          Target->typeWidthInBytesOnStack(SrcTy));
   const Operand *NewSrc = Src;
   if (auto *SrcVar = llvm::dyn_cast<Variable>(Src)) {
     int32_t NewRegNum = Variable::NoRegister;
     if (SrcVar->hasReg())
       NewRegNum = InstX86Base<Machine>::Traits::getGprForType(
           DestTy, SrcVar->getRegNum());
     if (SrcTy != DestTy)
       NewSrc = SrcVar->asType(DestTy, NewRegNum);
@@ skipping 458 matching lines @@
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(this->getSrc(0)->getType() == IceType_v8i16 ||
          this->getSrc(0)->getType() == IceType_v8i1 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<Machine>::Traits::TypeAttributes[this->getSrc(0)
                                                           ->getType()]
              .PackString << "\t";
   this->getSrc(1)->emit(Func);
   Str << ", ";
   this->getSrc(0)->emit(Func);
   Str << ", ";
   Variable *Dest = this->getDest();
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
   Dest->asType(IceType_i32, Dest->getRegNum())->emit(Func);
 }
 
 template <class Machine>
 void InstX86Pextr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 2);
   // pextrb and pextrd are SSE4.1 instructions.
   const Variable *Dest = this->getDest();
   Type DispatchTy = InstX86Base<Machine>::Traits::getInVectorElementType(
       this->getSrc(0)->getType());
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // pextrw must take a register dest. There is an SSE4.1 version that takes a
   // memory dest, but we aren't using it. For uniformity, just restrict them
   // all to have a register dest for now.
   assert(Dest->hasReg());
   // pextrw's Src(0) must be a register (both SSE4.1 and SSE2).
   assert(llvm::cast<Variable>(this->getSrc(0))->hasReg());
@@ skipping 11 matching lines @@
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(this->getSrcSize() == 3);
   // pinsrb and pinsrd are SSE4.1 instructions.
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(this->getDest()->getType() == IceType_v8i16 ||
          this->getDest()->getType() == IceType_v8i1 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   Str << "\t" << this->Opcode
       << InstX86Base<
              Machine>::Traits::TypeAttributes[this->getDest()->getType()]
              .PackString << "\t";
   this->getSrc(2)->emit(Func);
@@ skipping 17 matching lines @@
 }
 
 template <class Machine>
 void InstX86Pinsr<Machine>::emitIAS(const Cfg *Func) const {
   assert(this->getSrcSize() == 3);
   assert(this->getDest() == this->getSrc(0));
   // pinsrb and pinsrd are SSE4.1 instructions.
   const Operand *Src0 = this->getSrc(1);
   Type DispatchTy = Src0->getType();
   TargetLowering *Target = Func->getTarget();
+  (void)Target;
   assert(DispatchTy == IceType_i16 ||
          static_cast<typename InstX86Base<Machine>::Traits::TargetLowering *>(
              Target)
                  ->getInstructionSet() >= InstX86Base<Machine>::Traits::SSE4_1);
   // If src1 is a register, it should always be r32 (this should fall out from
   // the encodings for ByteRegs overlapping the encodings for r32), but we have
   // to make sure the register allocator didn't choose an 8-bit high register
   // like "ah".
   if (BuildDefs::asserts()) {
     if (auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
@@ skipping 414 matching lines @@
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "IACA_END";
 }
 
 } // end of namespace X86Internal
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX86BASEIMPL_H