- Annotate instructions that load objects from the ObjectPool or Thread.

runtime/vm/instructions_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm.h"
 #include "vm/cpu.h"
@@ skipping 151 matching lines @@
     ASSERT((instr & 0xfff00000) == 0xe3000000);  // movw reg, #imm_lo
     imm |= (instr & 0xf0000) >> 4;
     imm |= instr & 0xfff;
     *reg = static_cast<Register>((instr & 0xf000) >> 12);
     *value = imm;
   }
   return start;
 }
 
 
+static bool IsLoadWithOffset(int32_t instr, Register base,
+                             intptr_t* offset, Register* dst) {
+  if ((instr & 0xffff0000) == (0xe5900000 | (base << 16))) {
+    // ldr reg, [base, #+offset]
+    *offset = instr & 0xfff;
+    *dst = static_cast<Register>((instr & 0xf000) >> 12);
+    return true;
+  }
+  return false;
+}
+
+
 // Decodes a load sequence ending at 'end' (the last instruction of the load
 // sequence is the instruction before the one at end).  Returns a pointer to
 // the first instruction in the sequence.  Returns the register being loaded
 // and the index in the pool being read from in the output parameters 'reg'
 // and 'index' respectively.
 uword InstructionPattern::DecodeLoadWordFromPool(uword end,
                                                  Register* reg,
                                                  intptr_t* index) {
   uword start = end - Instr::kInstrSize;
   int32_t instr = Instr::At(start)->InstructionBits();
   intptr_t offset = 0;
-  if ((instr & 0xffff0000) == (0xe5950000 | (PP << 16))) {
-    // ldr reg, [pp, #+offset]
-    offset = instr & 0xfff;
-    *reg = static_cast<Register>((instr & 0xf000) >> 12);
+  if (IsLoadWithOffset(instr, PP, &offset, reg)) {
+    // ldr reg, [PP, #+offset]
   } else {
     ASSERT((instr & 0xfff00000) == 0xe5900000);  // ldr reg, [reg, #+offset]
     offset = instr & 0xfff;
     start -= Instr::kInstrSize;
     instr = Instr::At(start)->InstructionBits();
     if ((instr & 0xffff0000) == (0xe2850000 | (PP << 16))) {
       // add reg, pp, operand
       const intptr_t rot = (instr & 0xf00) >> 7;
       const intptr_t imm8 = instr & 0xff;
       offset += (imm8 >> rot) | (imm8 << (32 - rot));
       *reg = static_cast<Register>((instr & 0xf000) >> 12);
     } else {
       ASSERT((instr & 0xffff0000) == (0xe0800000 | (PP << 16)));
       // add reg, pp, reg
       end = DecodeLoadWordImmediate(end, reg, &offset);
     }
   }
   *index = ObjectPool::IndexFromOffset(offset);
   return start;
 }
 
 
+bool DecodeLoadObjectFromPoolOrThread(uword pc,
+                                      const Code& code,
+                                      Object* obj) {
+  ASSERT(code.ContainsInstructionAt(pc));
+
+  int32_t instr = Instr::At(pc)->InstructionBits();
+  intptr_t offset;
+  Register dst;
+  if (IsLoadWithOffset(instr, PP, &offset, &dst)) {
+    intptr_t index = ObjectPool::IndexFromOffset(offset);
+    const ObjectPool& pool = ObjectPool::Handle(code.object_pool());
+    if (pool.InfoAt(index) == ObjectPool::kTaggedObject) {
+      *obj = pool.ObjectAt(index);
+      return true;
+    }
+  } else if (IsLoadWithOffset(instr, THR, &offset, &dst)) {
+    return Thread::ObjectAtOffset(offset, obj);
+  }
+  // TODO(rmacnak): Sequence for loads beyond 12 bits.
+
+  return false;
+}
+
+
 RawICData* CallPattern::IcData() {
   if (ic_data_.IsNull()) {
     Register reg;
     InstructionPattern::DecodeLoadObject(ic_data_load_end_,
                                          object_pool_,
                                          &reg,
                                          &ic_data_);
     ASSERT(reg == R9);
   }
   return ic_data_.raw();
@@ skipping 112 matching lines @@
   } else {
     ASSERT(version == ARMv7);
     return bx_lr->InstructionBits() == instruction;
   }
   return false;
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM