Subzero: Use "pxor reg,reg" to load a floating-point scalar 0.0 value.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 11 matching lines @@
 #include "IceDefs.h"
 #include "IceELFObjectWriter.h"
 #include "IceGlobalInits.h"
 #include "IceInstVarIter.h"
 #include "IceLiveness.h"
 #include "IceOperand.h"
 #include "IcePhiLoweringImpl.h"
 #include "IceUtils.h"
 #include "llvm/Support/MathExtras.h"
 
+#include <cmath> // signbit()
 #include <stack>
 
 namespace Ice {
 namespace X86Internal {
 
 /// A helper class to ease the settings of RandomizationPoolingPause to disable
 /// constant blinding or pooling for some translation phases.
 class BoolFlagSaver {
   BoolFlagSaver() = delete;
   BoolFlagSaver(const BoolFlagSaver &) = delete;
@@ skipping 1867 matching lines @@
     _mov(T_Lo, Src0Lo);
     _mov(DestLo, T_Lo);
     _mov(T_Hi, Src0Hi);
     _mov(DestHi, T_Hi);
   } else {
     Operand *Src0Legal;
     if (Dest->hasReg()) {
       // If Dest already has a physical register, then only basic legalization
       // is needed, as the source operand can be a register, immediate, or
       // memory.
-      Src0Legal = legalize(Src0);
+      Src0Legal = legalize(Src0, Legal_Reg, Dest->getRegNum());
     } else {
       // If Dest could be a stack operand, then RI must be a physical register
       // or a scalar integer immediate.
       Src0Legal = legalize(Src0, Legal_Reg | Legal_Imm);
     }
     if (isVectorType(Dest->getType()))
       _movp(Dest, Src0Legal);
     else
       _mov(Dest, Src0Legal);
   }
@@ skipping 3370 matching lines @@
     return;
   }
 
   // Pause constant blinding or pooling, blinding or pooling will be done later
   // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
   PhiLowering::prelowerPhis32Bit<TargetX86Base<Machine>>(
       this, Context.getNode(), Func);
 }
 
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeZeroedRegister(Type Ty, int32_t RegNum) {
+  Variable *Reg = makeReg(Ty, RegNum);
+  switch (Ty) {
+  case IceType_i1:
+  case IceType_i8:
+  case IceType_i16:
+  case IceType_i32:
+  case IceType_i64:
+    // Conservatively do "mov reg, 0" to avoid modifying FLAGS.
+    _mov(Reg, Ctx->getConstantZero(Ty));
+    break;
+  case IceType_f32:
+  case IceType_f64:
+    Context.insert(InstFakeDef::create(Func, Reg));
+    // TODO(stichnot): Use xorps/xorpd instead of pxor.
+    _pxor(Reg, Reg);
+    break;
+  default:
+    // All vector types use the same pxor instruction.
+    assert(isVectorType(Ty));
+    Context.insert(InstFakeDef::create(Func, Reg));
+    _pxor(Reg, Reg);
+    break;
+  }
+  return Reg;
+}
+
 // There is no support for loading or emitting vector constants, so the vector
 // values returned from makeVectorOfZeros, makeVectorOfOnes, etc. are
 // initialized with register operations.
 //
 // TODO(wala): Add limited support for vector constants so that complex
 // initialization in registers is unnecessary.
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfZeros(Type Ty, int32_t RegNum) {
-  Variable *Reg = makeReg(Ty, RegNum);
-  // Insert a FakeDef, since otherwise the live range of Reg might be
-  // overestimated.
-  Context.insert(InstFakeDef::create(Func, Reg));
-  _pxor(Reg, Reg);
-  return Reg;
+  return makeZeroedRegister(Ty, RegNum);
 }
 
 template <class Machine>
 Variable *TargetX86Base<Machine>::makeVectorOfMinusOnes(Type Ty,
                                                         int32_t RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
   Context.insert(InstFakeDef::create(Func, MinusOnes));
   _pcmpeq(MinusOnes, MinusOnes);
   return MinusOnes;
@@ skipping 129 matching lines @@
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
+namespace {
+
+template <typename T> bool isPositiveZero(T Val) {
+  static_assert(std::is_floating_point<T>::value,
+                "Input type must be floating point");
+  return Val == 0 && !signbit(Val);
+}
+
+} // end of anonymous namespace
+
 template <class Machine>
 Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
                                           int32_t RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. If a physical register needs to be
   // explicitly disallowed, then new code will need to be written to force a
   // spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're not
@@ skipping 72 matching lines @@
     if (ConstantInteger32 *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
       }
     }
 
     // Convert a scalar floating point constant into an explicit memory
     // operand.
     if (isScalarFloatingType(Ty)) {
+      if (auto *ConstFloat = llvm::dyn_cast<ConstantFloat>(Const)) {
+        if (isPositiveZero(ConstFloat->getValue()))
+          return makeZeroedRegister(Ty, RegNum);
+      } else if (auto *ConstDouble = llvm::dyn_cast<ConstantDouble>(Const)) {
+        if (isPositiveZero(ConstDouble->getValue()))
+          return makeZeroedRegister(Ty, RegNum);
+      }
       Variable *Base = nullptr;
       std::string Buffer;
       llvm::raw_string_ostream StrBuf(Buffer);
       llvm::cast<Constant>(From)->emitPoolLabel(StrBuf, Ctx);
       llvm::cast<Constant>(From)->setShouldBePooled(true);
       Constant *Offset = Ctx->getConstantSym(0, StrBuf.str(), true);
       From = Traits::X86OperandMem::create(Func, Ty, Base, Offset);
     }
     bool NeedsReg = false;
     if (!(Allowed & Legal_Imm) && !isScalarFloatingType(Ty))
@@ skipping 402 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H