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Issue 1439053003: MIPS64: Implemented the RoundUint64ToFloat64 TurboFan operator for x64 and arm64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #if V8_TARGET_ARCH_MIPS64 7 #if V8_TARGET_ARCH_MIPS64
8 8
9 #include "src/base/division-by-constant.h" 9 #include "src/base/division-by-constant.h"
10 #include "src/bootstrapper.h" 10 #include "src/bootstrapper.h"
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1535 li(at, 0x41E00000); 1535 li(at, 0x41E00000);
1536 mtc1(zero_reg, scratch); 1536 mtc1(zero_reg, scratch);
1537 mthc1(at, scratch); 1537 mthc1(at, scratch);
1538 // Add it to fd. 1538 // Add it to fd.
1539 add_d(fd, fd, scratch); 1539 add_d(fd, fd, scratch);
1540 1540
1541 bind(&conversion_done); 1541 bind(&conversion_done);
1542 } 1542 }
1543 1543
1544 1544
1545 void MacroAssembler::Cvt_d_ul(FPURegister fd, FPURegister fs) {
1546 // Move the data from fs to t8.
1547 dmfc1(t8, fs);
1548 Cvt_d_ul(fd, t8);
1549 }
1550
1551
1552 void MacroAssembler::Cvt_d_ul(FPURegister fd, Register rs) {
1553 // Convert rs to a FP value in fd.
1554
1555 DCHECK(!rs.is(t9));
1556 DCHECK(!rs.is(at));
1557
1558 Label positive, conversion_done;
1559
1560 Branch(&positive, ge, rs, Operand(zero_reg));
1561
1562 // Rs >= 2^31.
1563 andi(t9, rs, 1);
1564 dsrl(rs, rs, 1);
1565 or_(t9, t9, rs);
1566 dmtc1(t9, fd);
1567 cvt_d_l(fd, fd);
1568 Branch(USE_DELAY_SLOT, &conversion_done);
1569 add_d(fd, fd, fd); // In delay slot.
1570
1571 bind(&positive);
1572 // Rs < 2^31, we can do simple conversion.
1573 dmtc1(rs, fd);
1574 cvt_d_l(fd, fd);
1575
1576 bind(&conversion_done);
1577 }
1578
1579
1545 void MacroAssembler::Round_l_d(FPURegister fd, FPURegister fs) { 1580 void MacroAssembler::Round_l_d(FPURegister fd, FPURegister fs) {
1546 round_l_d(fd, fs); 1581 round_l_d(fd, fs);
1547 } 1582 }
1548 1583
1549 1584
1550 void MacroAssembler::Floor_l_d(FPURegister fd, FPURegister fs) { 1585 void MacroAssembler::Floor_l_d(FPURegister fd, FPURegister fs) {
1551 floor_l_d(fd, fs); 1586 floor_l_d(fd, fs);
1552 } 1587 }
1553 1588
1554 1589
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6196 if (mag.shift > 0) sra(result, result, mag.shift); 6231 if (mag.shift > 0) sra(result, result, mag.shift);
6197 srl(at, dividend, 31); 6232 srl(at, dividend, 31);
6198 Addu(result, result, Operand(at)); 6233 Addu(result, result, Operand(at));
6199 } 6234 }
6200 6235
6201 6236
6202 } // namespace internal 6237 } // namespace internal
6203 } // namespace v8 6238 } // namespace v8
6204 6239
6205 #endif // V8_TARGET_ARCH_MIPS64 6240 #endif // V8_TARGET_ARCH_MIPS64
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