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Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1439053003: MIPS64: Implemented the RoundUint64ToFloat64 TurboFan operator for x64 and arm64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 59 matching lines...) Expand 10 before | Expand all | Expand 10 after
70 V(Mips64Float64RoundTruncate) \ 70 V(Mips64Float64RoundTruncate) \
71 V(Mips64Float64RoundUp) \ 71 V(Mips64Float64RoundUp) \
72 V(Mips64CvtSD) \ 72 V(Mips64CvtSD) \
73 V(Mips64CvtDS) \ 73 V(Mips64CvtDS) \
74 V(Mips64TruncWD) \ 74 V(Mips64TruncWD) \
75 V(Mips64TruncUwD) \ 75 V(Mips64TruncUwD) \
76 V(Mips64CvtDW) \ 76 V(Mips64CvtDW) \
77 V(Mips64CvtSL) \ 77 V(Mips64CvtSL) \
78 V(Mips64CvtDL) \ 78 V(Mips64CvtDL) \
79 V(Mips64CvtDUw) \ 79 V(Mips64CvtDUw) \
80 V(Mips64CvtDUl) \
80 V(Mips64Lb) \ 81 V(Mips64Lb) \
81 V(Mips64Lbu) \ 82 V(Mips64Lbu) \
82 V(Mips64Sb) \ 83 V(Mips64Sb) \
83 V(Mips64Lh) \ 84 V(Mips64Lh) \
84 V(Mips64Lhu) \ 85 V(Mips64Lhu) \
85 V(Mips64Sh) \ 86 V(Mips64Sh) \
86 V(Mips64Ld) \ 87 V(Mips64Ld) \
87 V(Mips64Lw) \ 88 V(Mips64Lw) \
88 V(Mips64Sw) \ 89 V(Mips64Sw) \
89 V(Mips64Sd) \ 90 V(Mips64Sd) \
(...skipping 33 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 #define TARGET_ADDRESSING_MODE_LIST(V) \ 124 #define TARGET_ADDRESSING_MODE_LIST(V) \
124 V(MRI) /* [%r0 + K] */ \ 125 V(MRI) /* [%r0 + K] */ \
125 V(MRR) /* [%r0 + %r1] */ 126 V(MRR) /* [%r0 + %r1] */
126 127
127 128
128 } // namespace compiler 129 } // namespace compiler
129 } // namespace internal 130 } // namespace internal
130 } // namespace v8 131 } // namespace v8
131 132
132 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 133 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
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