Subzero. ARM32. Improve constant lowering.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 494 matching lines @@
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: shr64BitSigned
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: shr64BitSigned
-; ARM32: lsr     [[T0:r[0-9]+]], r0, r2
-; ARM32: rsb     [[T1:r[0-9]+]], r2, #32
-; ARM32: orr     r0, [[T0]], r1, lsl [[T1]]
-; ARM32: sub     [[T2:r[0-9]+]], r2, #32
+; ARM32: lsr     [[T0:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
+; ARM32: rsb     [[T1:r[0-9]+]], r{{[0-9]+}}, #32
+; ARM32: orr     r{{[0-9]+}}, [[T0]], r{{[0-9]+}}, lsl [[T1]]
+; ARM32: sub     [[T2:r[0-9]+]], r{{[0-9]+}}, #32
 ; ARM32: cmp     [[T2]], #0
-; ARM32: asrge   r0, r1, [[T2]]
-; ARM32: asr     r{{[0-9]+}}, r1, r2
+; ARM32: asrge   r{{[0-9]+}}, r{{[0-9]+}}, [[T2]]
+; ARM32: asr     r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 
 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitSignedTrunc
 ; CHECK: shrd
 ; CHECK: sar
@@ skipping 1326 matching lines @@
 ; CHECK-LABEL: phi64Undef
 ; CHECK: mov {{.*}},0x0
 ; CHECK: mov {{.*}},0x0
 ; OPTM1-LABEL: phi64Undef
 ; OPTM1: mov {{.*}},0x0
 ; OPTM1: mov {{.*}},0x0
 ; ARM32-LABEL: phi64Undef
 ; ARM32: mov {{.*}} #0
 ; ARM32: mov {{.*}} #0