Subzero. ARM32. Improve constant lowering.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 22 matching lines @@
   OperandARM32() = delete;
   OperandARM32(const OperandARM32 &) = delete;
   OperandARM32 &operator=(const OperandARM32 &) = delete;
 
 public:
   enum OperandKindARM32 {
     k__Start = Operand::kTarget,
     kMem,
     kFlexStart,
     kFlexImm = kFlexStart,
+    kFlexFpImm,
+    kFlexFpZero,
     kFlexReg,
     kFlexEnd = kFlexReg
   };
 
   enum ShiftKind {
     kNoShift = -1,
 #define X(enum, emit) enum,
     ICEINSTARM32SHIFT_TABLE
 #undef X
   };
@@ skipping 145 matching lines @@
   uint32_t getImm() const { return Imm; }
   uint32_t getRotateAmt() const { return RotateAmt; }
 
 private:
   OperandARM32FlexImm(Cfg *Func, Type Ty, uint32_t Imm, uint32_t RotateAmt);
 
   uint32_t Imm;
   uint32_t RotateAmt;
 };
 
+/// Modified Floating-point constant.
+class OperandARM32FlexFpImm : public OperandARM32Flex {
+  OperandARM32FlexFpImm() = delete;
+  OperandARM32FlexFpImm(const OperandARM32FlexFpImm &) = delete;
+  OperandARM32FlexFpImm &operator=(const OperandARM32FlexFpImm &) = delete;
+
+public:
+  static OperandARM32FlexFpImm *create(Cfg *Func, Type Ty,
+                                       uint32_t ModifiedImm) {
+    return new (Func->allocate<OperandARM32FlexFpImm>())
+        OperandARM32FlexFpImm(Func, Ty, ModifiedImm);
+  }
+
+  void emit(const Cfg *Func) const override;
+  using OperandARM32::dump;
+  void dump(const Cfg *Func, Ostream &Str) const override;
+
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == static_cast<OperandKind>(kFlexFpImm);
+  }
+
+  static bool canHoldImm(Operand *C, uint32_t *ModifiedImm);
+
+private:
+  OperandARM32FlexFpImm(Cfg *Func, Type Ty, uint32_t ModifiedImm);
+
+  uint32_t ModifiedImm;
+};
+
+/// An operand for representing the 0.0 immediate in vcmp.
+class OperandARM32FlexFpZero : public OperandARM32Flex {
+  OperandARM32FlexFpZero() = delete;
+  OperandARM32FlexFpZero(const OperandARM32FlexFpZero &) = delete;
+  OperandARM32FlexFpZero &operator=(const OperandARM32FlexFpZero &) = delete;
+
+public:
+  static OperandARM32FlexFpZero *create(Cfg *Func, Type Ty) {
+    return new (Func->allocate<OperandARM32FlexFpZero>())
+        OperandARM32FlexFpZero(Func, Ty);
+  }
+
+  void emit(const Cfg *Func) const override;
+  using OperandARM32::dump;
+  void dump(const Cfg *Func, Ostream &Str) const override;
+
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == static_cast<OperandKind>(kFlexFpZero);
+  }
+
+private:
+  OperandARM32FlexFpZero(Cfg *Func, Type Ty);
+};
+
 /// Shifted register variant.
 class OperandARM32FlexReg : public OperandARM32Flex {
   OperandARM32FlexReg() = delete;
   OperandARM32FlexReg(const OperandARM32FlexReg &) = delete;
   OperandARM32FlexReg &operator=(const OperandARM32FlexReg &) = delete;
 
 public:
   /// Register with immediate/reg shift amount and shift operation.
   static OperandARM32FlexReg *create(Cfg *Func, Type Ty, Variable *Reg,
                                      ShiftKind ShiftOp, Operand *ShiftAmt) {
@@ skipping 64 matching lines @@
   enum InstKindARM32 {
     k__Start = Inst::Target,
     Adc,
     Add,
     Adjuststack,
     And,
     Asr,
     Bic,
     Br,
     Call,
+    Cmn,
     Cmp,
     Clz,
     Dmb,
     Eor,
     Label,
     Ldr,
     Ldrex,
     Lsl,
     Lsr,
     Mla,
     Mls,
     Mov,
     Movt,
     Movw,
     Mul,
     Mvn,
     Orr,
     Pop,
     Push,
     Rbit,
     Ret,
     Rev,
     Rsb,
+    Rsc,
     Sbc,
     Sdiv,
     Str,
     Strex,
     Sub,
     Sxt,
     Trap,
     Tst,
     Udiv,
     Umull,
     Uxt,
     Vabs,
     Vadd,
     Vcmp,
     Vcvt,
     Vdiv,
+    Veor,
     Vmrs,
     Vmul,
     Vsqrt,
     Vsub
   };
 
   static constexpr size_t InstSize = sizeof(uint32_t);
 
   static const char *getWidthString(Type Ty);
   static const char *getVecWidthString(Type Ty);
@@ skipping 261 matching lines @@
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << (SetFlags ? ".s " : " ");
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
 private:
   InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0,
                         Operand *Src1, CondARM32::Cond Predicate, bool SetFlags)
       : InstARM32Pred(Func, K, 2, Dest, Predicate), SetFlags(SetFlags) {
+    HasSideEffects = SetFlags;
     addSource(Src0);
     addSource(Src1);
   }
 
   static const char *Opcode;
   bool SetFlags;
 };
 
 /// Instructions of the form x := y op z, for vector/FP. We leave these as
 /// unconditional: "ARM deprecates the conditional execution of any instruction
@@ skipping 112 matching lines @@
     dumpOpcodePred(Str, Opcode, getSrc(0)->getType());
     Str << " ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
 private:
   InstARM32CmpLike(Cfg *Func, Variable *Src0, Operand *Src1,
                    CondARM32::Cond Predicate)
       : InstARM32Pred(Func, K, 2, nullptr, Predicate) {
+    HasSideEffects = true;
     addSource(Src0);
     addSource(Src1);
   }
 
   static const char *Opcode;
 };
 
 using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
 using InstARM32Add = InstARM32ThreeAddrGPR<InstARM32::Add>;
 using InstARM32And = InstARM32ThreeAddrGPR<InstARM32::And>;
 using InstARM32Asr = InstARM32ThreeAddrGPR<InstARM32::Asr>;
 using InstARM32Bic = InstARM32ThreeAddrGPR<InstARM32::Bic>;
 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
 using InstARM32Lsl = InstARM32ThreeAddrGPR<InstARM32::Lsl>;
 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
 using InstARM32Mul = InstARM32ThreeAddrGPR<InstARM32::Mul>;
 using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
 using InstARM32Rsb = InstARM32ThreeAddrGPR<InstARM32::Rsb>;
+using InstARM32Rsc = InstARM32ThreeAddrGPR<InstARM32::Rsc>;
 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
+using InstARM32Veor = InstARM32ThreeAddrFP<InstARM32::Veor>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
 using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
 using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;
 /// MovT leaves the bottom bits alone so dest is also a source. This helps
 /// indicate that a previous MovW setting dest is not dead code.
 using InstARM32Movt = InstARM32TwoAddrGPR<InstARM32::Movt>;
 using InstARM32Movw = InstARM32UnaryopGPR<InstARM32::Movw, false>;
 using InstARM32Clz = InstARM32UnaryopGPR<InstARM32::Clz, false>;
 using InstARM32Mvn = InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 using InstARM32Rbit = InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 using InstARM32Rev = InstARM32UnaryopGPR<InstARM32::Rev, false>;
 // Technically, the uxt{b,h} and sxt{b,h} instructions have a rotation operand
 // as well (rotate source by 8, 16, 24 bits prior to extending), but we aren't
 // using that for now, so just model as a Unaryop.
 using InstARM32Sxt = InstARM32UnaryopGPR<InstARM32::Sxt, true>;
 using InstARM32Uxt = InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 using InstARM32Vsqrt = InstARM32UnaryopFP<InstARM32::Vsqrt>;
 using InstARM32Mla = InstARM32FourAddrGPR<InstARM32::Mla>;
 using InstARM32Mls = InstARM32FourAddrGPR<InstARM32::Mls>;
+using InstARM32Cmn = InstARM32CmpLike<InstARM32::Cmn>;
 using InstARM32Cmp = InstARM32CmpLike<InstARM32::Cmp>;
 using InstARM32Tst = InstARM32CmpLike<InstARM32::Tst>;
 
 // InstARM32Label represents an intra-block label that is the target of an
 // intra-block branch. The offset between the label and the branch must be fit
 // in the instruction immediate (considered "near").
 class InstARM32Label : public InstARM32 {
   InstARM32Label() = delete;
   InstARM32Label(const InstARM32Label &) = delete;
   InstARM32Label &operator=(const InstARM32Label &) = delete;
@@ skipping 373 matching lines @@
   InstARM32Vcmp() = delete;
   InstARM32Vcmp(const InstARM32Vcmp &) = delete;
   InstARM32Vcmp &operator=(const InstARM32Vcmp &) = delete;
 
 public:
   static InstARM32Vcmp *create(Cfg *Func, Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Vcmp>())
         InstARM32Vcmp(Func, Src0, Src1, Predicate);
   }
+  static InstARM32Vcmp *create(Cfg *Func, Variable *Src0,
+                               OperandARM32FlexFpZero *Src1,
+                               CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32Vcmp>())
+        InstARM32Vcmp(Func, Src0, Src1, Predicate);
+  }
   void emit(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Vcmp); }
 
 private:
-  InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
+  InstARM32Vcmp(Cfg *Func, Variable *Src0, Operand *Src1,
                 CondARM32::Cond Predicate);
 };
 
 /// Copies the FP Status and Control Register the core flags.
 class InstARM32Vmrs final : public InstARM32Pred {
   InstARM32Vmrs() = delete;
   InstARM32Vmrs(const InstARM32Vmrs &) = delete;
   InstARM32Vmrs &operator=(const InstARM32Vmrs &) = delete;
 
 public:
@@ skipping 49 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H