Subzero. ARM32. Improve constant lowering.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 266 matching lines @@
     uint32_t Imm8 = Utils::rotateLeft32(Immediate, 2 * Rot);
     if (Imm8 <= 0xFF) {
       *RotateAmt = Rot;
       *Immed_8 = Imm8;
       return true;
     }
   }
   return false;
 }
 
+OperandARM32FlexFpImm::OperandARM32FlexFpImm(Cfg * /*Func*/, Type Ty,
+                                             uint32_t ModifiedImm)
+    : OperandARM32Flex(kFlexFpImm, Ty), ModifiedImm(ModifiedImm) {}
+
+bool OperandARM32FlexFpImm::canHoldImm(Operand *C, uint32_t *ModifiedImm) {
+  switch (C->getType()) {
+  default:
+    llvm::report_fatal_error("Unhandled fp constant type.");
+  case IceType_f32: {
+    // We violate llvm naming conventions a bit here so that the constants are
+    // named after the bit fields they represent. See "A7.5.1 Operation of
+    // modified immediate constants, Floating-point" in the ARM ARM.
+    static constexpr uint32_t a = 0x80000000u;
+    static constexpr uint32_t B = 0x40000000;
+    static constexpr uint32_t bbbbb = 0x3E000000;
+    static constexpr uint32_t cdefgh = 0x01F80000;
+    static constexpr uint32_t AllowedBits = a | B | bbbbb | cdefgh;
+    static_assert(AllowedBits == 0xFFF80000u,
+                  "Invalid mask for f32 modified immediates.");
+    const float F32 = llvm::cast<ConstantFloat>(C)->getValue();
+    const uint32_t I32 = *reinterpret_cast<const uint32_t *>(&F32);
+    if (I32 & ~AllowedBits) {
+      // constant has disallowed bits.
+      return false;
+    }
+
+    if ((I32 & bbbbb) != bbbbb && (I32 & bbbbb)) {
+      // not all bbbbb bits are 0 or 1.
+      return false;
+    }
+
+    if (((I32 & B) != 0) == ((I32 & bbbbb) != 0)) {
+      // B ^ b = 0;
+      return false;
+    }
+
+    *ModifiedImm = ((I32 & a) ? 0x80 : 0x00) | ((I32 & bbbbb) ? 0x40 : 0x00) |
+                   ((I32 & cdefgh) >> 19);
+    return true;
+  }
+  case IceType_f64: {
+    static constexpr uint32_t a = 0x80000000u;
+    static constexpr uint32_t B = 0x40000000;
+    static constexpr uint32_t bbbbbbbb = 0x3FC00000;
+    static constexpr uint32_t cdefgh = 0x003F0000;
+    static constexpr uint32_t AllowedBits = a | B | bbbbbbbb | cdefgh;
+    static_assert(AllowedBits == 0xFFFF0000u,
+                  "Invalid mask for f64 modified immediates.");
+    const double F64 = llvm::cast<ConstantDouble>(C)->getValue();
+    const uint64_t I64 = *reinterpret_cast<const uint64_t *>(&F64);
+    if (I64 & 0xFFFFFFFFu) {
+      // constant has disallowed bits.
+      return false;
+    }
+    const uint32_t I32 = I64 >> 32;
+
+    if (I32 & ~AllowedBits) {
+      // constant has disallowed bits.
+      return false;
+    }
+
+    if ((I32 & bbbbbbbb) != bbbbbbbb && (I32 & bbbbbbbb)) {
+      // not all bbbbb bits are 0 or 1.
+      return false;
+    }
+
+    if (((I32 & B) != 0) == ((I32 & bbbbbbbb) != 0)) {
+      // B ^ b = 0;
+      return false;
+    }
+
+    *ModifiedImm = ((I32 & a) ? 0x80 : 0x00) |
+                   ((I32 & bbbbbbbb) ? 0x40 : 0x00) | ((I32 & cdefgh) >> 16);
+    return true;
+  }
+  }
+}
+
+OperandARM32FlexFpZero::OperandARM32FlexFpZero(Cfg * /*Func*/, Type Ty)
+    : OperandARM32Flex(kFlexFpZero, Ty) {}
+
 OperandARM32FlexReg::OperandARM32FlexReg(Cfg *Func, Type Ty, Variable *Reg,
                                          ShiftKind ShiftOp, Operand *ShiftAmt)
     : OperandARM32Flex(kFlexReg, Ty), Reg(Reg), ShiftOp(ShiftOp),
       ShiftAmt(ShiftAmt) {
   NumVars = 1;
   Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt);
   if (ShiftVar)
     ++NumVars;
   Vars = Func->allocateArrayOf<Variable *>(NumVars);
   Vars[0] = Reg;
@@ skipping 253 matching lines @@
 }
 
 template <> void InstARM32Tst::emitIAS(const Cfg *Func) const {
   assert(getSrcSize() == 2);
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   Asm->tst(getSrc(0), getSrc(1), getPredicate());
   if (Asm->needsTextFixup())
     emitUsingTextFixup(Func);
 }
 
-InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
+InstARM32Vcmp::InstARM32Vcmp(Cfg *Func, Variable *Src0, Operand *Src1,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vcmp, 2, nullptr, Predicate) {
+  HasSideEffects = true;
   addSource(Src0);
   addSource(Src1);
 }
 
 InstARM32Vmrs::InstARM32Vmrs(Cfg *Func, CondARM32::Cond Predicate)
-    : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {}
+    : InstARM32Pred(Func, InstARM32::Vmrs, 0, nullptr, Predicate) {
+  HasSideEffects = true;
+}
 
 InstARM32Vabs::InstARM32Vabs(Cfg *Func, Variable *Dest, Variable *Src,
                              CondARM32::Cond Predicate)
     : InstARM32Pred(Func, InstARM32::Vabs, 1, Dest, Predicate) {
   addSource(Src);
 }
 
 InstARM32Dmb::InstARM32Dmb(Cfg *Func)
     : InstARM32Pred(Func, InstARM32::Dmb, 0, nullptr, CondARM32::AL) {}
 
@@ skipping 19 matching lines @@
 template <> const char *InstARM32Add::Opcode = "add";
 template <> const char *InstARM32And::Opcode = "and";
 template <> const char *InstARM32Asr::Opcode = "asr";
 template <> const char *InstARM32Bic::Opcode = "bic";
 template <> const char *InstARM32Eor::Opcode = "eor";
 template <> const char *InstARM32Lsl::Opcode = "lsl";
 template <> const char *InstARM32Lsr::Opcode = "lsr";
 template <> const char *InstARM32Mul::Opcode = "mul";
 template <> const char *InstARM32Orr::Opcode = "orr";
 template <> const char *InstARM32Rsb::Opcode = "rsb";
+template <> const char *InstARM32Rsc::Opcode = "rsc";
 template <> const char *InstARM32Sbc::Opcode = "sbc";
 template <> const char *InstARM32Sdiv::Opcode = "sdiv";
 template <> const char *InstARM32Sub::Opcode = "sub";
 template <> const char *InstARM32Udiv::Opcode = "udiv";
 // FP
 template <> const char *InstARM32Vadd::Opcode = "vadd";
 template <> const char *InstARM32Vdiv::Opcode = "vdiv";
 template <> const char *InstARM32Vmul::Opcode = "vmul";
+template <> const char *InstARM32Veor::Opcode = "veor";
 template <> const char *InstARM32Vsub::Opcode = "vsub";
 // Four-addr ops
 template <> const char *InstARM32Mla::Opcode = "mla";
 template <> const char *InstARM32Mls::Opcode = "mls";
 // Cmp-like ops
+template <> const char *InstARM32Cmn::Opcode = "cmn";
 template <> const char *InstARM32Cmp::Opcode = "cmp";
 template <> const char *InstARM32Tst::Opcode = "tst";
 
 void InstARM32::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "[ARM32] ";
   Inst::dump(Func);
 }
@@ skipping 1063 matching lines @@
 }
 
 void OperandARM32FlexImm::dump(const Cfg * /* Func */, Ostream &Str) const {
   if (!BuildDefs::dump())
     return;
   uint32_t Imm = getImm();
   uint32_t RotateAmt = getRotateAmt();
   Str << "#(" << Imm << " ror 2*" << RotateAmt << ")";
 }
 
+namespace {
+static constexpr uint32_t a = 0x80;
+static constexpr uint32_t b = 0x40;
+static constexpr uint32_t cdefgh = 0x3F;
+static constexpr uint32_t AllowedBits = a | b | cdefgh;
+static_assert(AllowedBits == 0xFF,
+              "Invalid mask for f32/f64 constant rematerialization.");
+
+// There's no loss in always returning the modified immediate as float.
+// TODO(jpp): returning a double causes problems when outputting the constants
+// for filetype=asm. Why?
+float materializeFloatImmediate(uint32_t ModifiedImm) {
+  const uint32_t Ret = ((ModifiedImm & a) ? 0x80000000 : 0) |
+                       ((ModifiedImm & b) ? 0x3E000000 : 0x40000000) |
+                       ((ModifiedImm & cdefgh) << 19);
+  return *reinterpret_cast<const float *>(&Ret);
+}
+
+} // end of anonymous namespace
+
+void OperandARM32FlexFpImm::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  switch (Ty) {
+  default:
+    llvm::report_fatal_error("Invalid flex fp imm type.");
+  case IceType_f64:
+  case IceType_f32:
+    Str << "#" << materializeFloatImmediate(ModifiedImm)
+        << " @ Modified: " << ModifiedImm;
+    break;
+  }
+}
+
+void OperandARM32FlexFpImm::dump(const Cfg * /*Func*/, Ostream &Str) const {
+  if (!BuildDefs::dump())
+    return;
+  Str << "#" << materializeFloatImmediate(ModifiedImm)
+      << InstARM32::getVecWidthString(Ty);
+}
+
+void OperandARM32FlexFpZero::emit(const Cfg *Func) const {
+  if (!BuildDefs::dump())
+    return;
+  Ostream &Str = Func->getContext()->getStrEmit();
+  switch (Ty) {
+  default:
+    llvm::report_fatal_error("Invalid flex fp imm type.");
+  case IceType_f64:
+  case IceType_f32:
+    Str << "#0.0";
+  }
+}
+
+void OperandARM32FlexFpZero::dump(const Cfg * /*Func*/, Ostream &Str) const {
+  if (!BuildDefs::dump())
+    return;
+  Str << "#0.0" << InstARM32::getVecWidthString(Ty);
+}
+
 void OperandARM32FlexReg::emit(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   getReg()->emit(Func);
   if (getShiftOp() != kNoShift) {
     Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
     getShiftAmt()->emit(Func);
   }
 }
@@ skipping 20 matching lines @@
 template class InstARM32ThreeAddrGPR<InstARM32::Add>;
 template class InstARM32ThreeAddrGPR<InstARM32::And>;
 template class InstARM32ThreeAddrGPR<InstARM32::Asr>;
 template class InstARM32ThreeAddrGPR<InstARM32::Bic>;
 template class InstARM32ThreeAddrGPR<InstARM32::Eor>;
 template class InstARM32ThreeAddrGPR<InstARM32::Lsl>;
 template class InstARM32ThreeAddrGPR<InstARM32::Lsr>;
 template class InstARM32ThreeAddrGPR<InstARM32::Mul>;
 template class InstARM32ThreeAddrGPR<InstARM32::Orr>;
 template class InstARM32ThreeAddrGPR<InstARM32::Rsb>;
+template class InstARM32ThreeAddrGPR<InstARM32::Rsc>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sub>;
 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 
 template class InstARM32ThreeAddrFP<InstARM32::Vadd>;
 template class InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 template class InstARM32ThreeAddrFP<InstARM32::Vmul>;
+template class InstARM32ThreeAddrFP<InstARM32::Veor>;
 template class InstARM32ThreeAddrFP<InstARM32::Vsub>;
 
 template class InstARM32LoadBase<InstARM32::Ldr>;
 template class InstARM32LoadBase<InstARM32::Ldrex>;
 
 template class InstARM32TwoAddrGPR<InstARM32::Movt>;
 
 template class InstARM32UnaryopGPR<InstARM32::Movw, false>;
 template class InstARM32UnaryopGPR<InstARM32::Clz, false>;
 template class InstARM32UnaryopGPR<InstARM32::Mvn, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rbit, false>;
 template class InstARM32UnaryopGPR<InstARM32::Rev, false>;
 template class InstARM32UnaryopGPR<InstARM32::Sxt, true>;
 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
+template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace Ice