Subzero. ARM32. Improve constant lowering.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 22 matching lines @@
   OperandARM32() = delete;
   OperandARM32(const OperandARM32 &) = delete;
   OperandARM32 &operator=(const OperandARM32 &) = delete;
 
 public:
   enum OperandKindARM32 {
     k__Start = Operand::kTarget,
     kMem,
     kFlexStart,
     kFlexImm = kFlexStart,
+    kFlexFpImm,
+    kFlexFpZero,
     kFlexReg,
     kFlexEnd = kFlexReg
   };
 
   enum ShiftKind {
     kNoShift = -1,
 #define X(enum, emit) enum,
     ICEINSTARM32SHIFT_TABLE
 #undef X
   };
@@ skipping 145 matching lines @@
   uint32_t getImm() const { return Imm; }
   uint32_t getRotateAmt() const { return RotateAmt; }
 
 private:
   OperandARM32FlexImm(Cfg *Func, Type Ty, uint32_t Imm, uint32_t RotateAmt);
 
   uint32_t Imm;
   uint32_t RotateAmt;
 };
 
+/// Modified Floating-point constant.
+class OperandARM32FlexFpImm : public OperandARM32Flex {
+  OperandARM32FlexFpImm() = delete;
+  OperandARM32FlexFpImm(const OperandARM32FlexFpImm &) = delete;
+  OperandARM32FlexFpImm &operator=(const OperandARM32FlexFpImm &) = delete;
+
+public:
+  static OperandARM32FlexFpImm *create(Cfg *Func, Type Ty,
+                                       uint32_t ModifiedImm) {
+    return new (Func->allocate<OperandARM32FlexFpImm>())
+        OperandARM32FlexFpImm(Func, Ty, ModifiedImm);
+  }
+
+  void emit(const Cfg *Func) const override;
+  using OperandARM32::dump;

[sehr, 2015/11/13 21:56:29]

What does this using do?

[John, 2015/11/14 00:00:38]

Operand::dump is overloaded. The

 OperandARM32FlexFpImm::dump(const Cfg*, Ostream &) below 

defined below hides the two overloads in the base case. Thus, we need to tell
the compiler that those methods are available. (This is why Google3 coding style
forbids overloaded virtual methods)

[Jim Stichnoth, 2015/11/16 23:06:26]

Interesting.  Maybe we (I) should later take a pass over dump() and remove its
silly overloads.

+  void dump(const Cfg *Func, Ostream &Str) const override;
+
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == static_cast<OperandKind>(kFlexFpImm);
+  }
+
+  static bool canHoldImm(Operand *C, uint32_t *ModifiedImm);
+
+private:
+  OperandARM32FlexFpImm(Cfg *Func, Type Ty, uint32_t ModifiedImm);
+
+  uint32_t ModifiedImm;
+};
+
+/// An operand for representing the 0.0 immediate in vcmp.
+class OperandARM32FlexFpZero : public OperandARM32Flex {
+  OperandARM32FlexFpZero() = delete;
+  OperandARM32FlexFpZero(const OperandARM32FlexFpZero &) = delete;
+  OperandARM32FlexFpZero &operator=(const OperandARM32FlexFpZero &) = delete;
+
+public:
+  static OperandARM32FlexFpZero *create(Cfg *Func, Type Ty) {
+    return new (Func->allocate<OperandARM32FlexFpZero>())
+        OperandARM32FlexFpZero(Func, Ty);
+  }
+
+  void emit(const Cfg *Func) const override;
+  using OperandARM32::dump;
+  void dump(const Cfg *Func, Ostream &Str) const override;
+
+  static bool classof(const Operand *Operand) {
+    return Operand->getKind() == static_cast<OperandKind>(kFlexFpZero);
+  }
+
+private:
+  OperandARM32FlexFpZero(Cfg *Func, Type Ty);
+};
+
 /// Shifted register variant.
 class OperandARM32FlexReg : public OperandARM32Flex {
   OperandARM32FlexReg() = delete;
   OperandARM32FlexReg(const OperandARM32FlexReg &) = delete;
   OperandARM32FlexReg &operator=(const OperandARM32FlexReg &) = delete;
 
 public:
   /// Register with immediate/reg shift amount and shift operation.
   static OperandARM32FlexReg *create(Cfg *Func, Type Ty, Variable *Reg,
                                      ShiftKind ShiftOp, Operand *ShiftAmt) {
@@ skipping 87 matching lines @@
     Movw,
     Mul,
     Mvn,
     Orr,
     Pop,
     Push,
     Rbit,
     Ret,
     Rev,
     Rsb,
+    Rsc,
     Sbc,
     Sdiv,
     Str,
     Strex,
     Sub,
     Sxt,
     Trap,
     Tst,
     Udiv,
     Umull,
@@ skipping 277 matching lines @@
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << (SetFlags ? ".s " : " ");
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
 private:
   InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0,
                         Operand *Src1, CondARM32::Cond Predicate, bool SetFlags)
       : InstARM32Pred(Func, K, 2, Dest, Predicate), SetFlags(SetFlags) {
+    HasSideEffects = SetFlags;
     addSource(Src0);
     addSource(Src1);
   }
 
   static const char *Opcode;
   bool SetFlags;
 };
 
 /// Instructions of the form x := y op z, for vector/FP. We leave these as
 /// unconditional: "ARM deprecates the conditional execution of any instruction
@@ skipping 112 matching lines @@
     dumpOpcodePred(Str, Opcode, getSrc(0)->getType());
     Str << " ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
 private:
   InstARM32CmpLike(Cfg *Func, Variable *Src0, Operand *Src1,
                    CondARM32::Cond Predicate)
       : InstARM32Pred(Func, K, 2, nullptr, Predicate) {
+    HasSideEffects = true;
     addSource(Src0);
     addSource(Src1);
   }
 
   static const char *Opcode;
 };
 
 using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
 using InstARM32Add = InstARM32ThreeAddrGPR<InstARM32::Add>;
 using InstARM32And = InstARM32ThreeAddrGPR<InstARM32::And>;
 using InstARM32Asr = InstARM32ThreeAddrGPR<InstARM32::Asr>;
 using InstARM32Bic = InstARM32ThreeAddrGPR<InstARM32::Bic>;
 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
 using InstARM32Lsl = InstARM32ThreeAddrGPR<InstARM32::Lsl>;
 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
 using InstARM32Mul = InstARM32ThreeAddrGPR<InstARM32::Mul>;
 using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
 using InstARM32Rsb = InstARM32ThreeAddrGPR<InstARM32::Rsb>;
+using InstARM32Rsc = InstARM32ThreeAddrGPR<InstARM32::Rsc>;
 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
 using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
 using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;
@@ skipping 399 matching lines @@
   InstARM32Vcmp() = delete;
   InstARM32Vcmp(const InstARM32Vcmp &) = delete;
   InstARM32Vcmp &operator=(const InstARM32Vcmp &) = delete;
 
 public:
   static InstARM32Vcmp *create(Cfg *Func, Variable *Src0, Variable *Src1,
                                CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Vcmp>())
         InstARM32Vcmp(Func, Src0, Src1, Predicate);
   }
+  static InstARM32Vcmp *create(Cfg *Func, Variable *Src0,
+                               OperandARM32FlexFpZero *Src1,
+                               CondARM32::Cond Predicate) {
+    return new (Func->allocate<InstARM32Vcmp>())
+        InstARM32Vcmp(Func, Src0, Src1, Predicate);
+  }
   void emit(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Vcmp); }
 
 private:
-  InstARM32Vcmp(Cfg *Func, Variable *Src0, Variable *Src1,
+  InstARM32Vcmp(Cfg *Func, Variable *Src0, Operand *Src1,
                 CondARM32::Cond Predicate);
 };
 
 /// Copies the FP Status and Control Register the core flags.
 class InstARM32Vmrs final : public InstARM32Pred {
   InstARM32Vmrs() = delete;
   InstARM32Vmrs(const InstARM32Vmrs &) = delete;
   InstARM32Vmrs &operator=(const InstARM32Vmrs &) = delete;
 
 public:
@@ skipping 49 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H