Improve bool folding

tests_lit/llvm2ice_tests/fp.cmp.ll

 ; This tries to be a comprehensive test of f32 and f64 compare operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.

[Jim Stichnoth, 2015/11/11 14:05:20]

This intro is by now almost entirely untrue. :)

It never really was a comprehensive test because it only 6 of the 16 fcmp
conditions - the ones accessible in C.

And there now are OPTM1 lines (well, CHECK-OM1).

[sehr, 2015/11/13 06:00:52]

I have removed the comment.

 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN:   -allow-externally-defined-symbols | FileCheck %s
+; RUN:   -allow-externally-defined-symbols | FileCheck %s \
+; RUN:   --check-prefix=CHECK-OM1
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -O2 \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
 ; RUN:   --check-prefix=ARM32 --check-prefix=ARM32-O2
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -Om1 \
 ; RUN:   -allow-externally-defined-symbols \
@@ skipping 15 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; CHECK-LABEL: fcmpEq
 ; CHECK: ucomiss
-; CHECK: jne
+; CHECK-NEXT: jne
+; CHECK-NEXT: jp
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK: ucomisd
+; CHECK-NEXT: jne
 ; CHECK-NEXT: jp
 ; CHECK: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK: jne
-; CHECK-NEXT: jp
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpEq
+; CHECK-OM1: ucomiss
+; CHECK-OM1: jne
+; CHECK-OM1-NEXT: jp
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1: jne
+; CHECK-NEXT-OM1: jp
 ; ARM32-LABEL: fcmpEq
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: movne [[R0:r[0-9]+]], #0
 ; ARM32-OM1: moveq [[R0]], #1
 ; ARM32-O2: bne
 ; ARM32: bl func
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: movne [[R1:r[0-9]+]], #0
@@ skipping 17 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; CHECK-LABEL: fcmpNe
 ; CHECK: ucomiss
-; CHECK: jne
+; CHECK-NEXT: jne
 ; CHECK-NEXT: jp
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jmp
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
-; CHECK: jne
+; CHECK-NEXT: jne
 ; CHECK-NEXT: jp
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jmp
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpNe
+; CHECK-OM1: ucomiss
+; CHECK-OM1: jne
+; CHECK-OM1: jp
+; CHECK-OM1: jmp
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1: jne
+; CHECK-OM1: jp
+; CHECK-OM1: jmp
+; CHECK-OM1: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpNe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: moveq [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movne [[R0]], #1
 ; ARM32-O2: beq
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: moveq [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movne [[R1]], #1
@@ skipping 14 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; CHECK-LABEL: fcmpGt
 ; CHECK: ucomiss
-; CHECK: seta
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jbe
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
-; CHECK: seta
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jbe
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpGt
+; CHECK-OM1: ucomiss
+; CHECK-OM1: seta
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1: seta
+; CHECK-OM1: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpGt
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: movle [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movgt [[R0]], #1
 ; ARM32-O2: ble
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: movle [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movgt [[R1]], #1
@@ skipping 14 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.end, %if.then2
   ret void
 }
 ; CHECK-LABEL: fcmpGe
 ; CHECK: ucomiss
-; CHECK: setb
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jb
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
-; CHECK: setb
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jb
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpGe
+; CHECK-OM1: ucomiss
+; CHECK-OM1-NEXT: setb
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1-NEXT: setb
+; CHECK-OM1: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpGe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: movge [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movlt [[R0]], #1
 ; ARM32-O2: blt
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: movge [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movlt [[R1]], #1
@@ skipping 14 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.then2, %if.end
   ret void
 }
 ; CHECK-LABEL: fcmpLt
 ; CHECK: ucomiss
-; CHECK: seta
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jbe
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
-; CHECK: seta
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jbe
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpLt
+; CHECK-OM1: ucomiss
+; CHECK-OM1-NEXT: seta
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1-NEXT: seta
+; CHECK-OM1: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpLt
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: movpl [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movmi [[R0]], #1
 ; ARM32-O2: bpl
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: movpl [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movmi [[R1]], #1
@@ skipping 14 matching lines @@
 
 if.then2:                                         ; preds = %if.end
   call void @func()
   br label %if.end3
 
 if.end3:                                          ; preds = %if.end, %if.then2
   ret void
 }
 ; CHECK-LABEL: fcmpLe
 ; CHECK: ucomiss
-; CHECK: setb
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jb
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
 ; CHECK: ucomisd
-; CHECK: setb
-; CHECK: call {{.*}} R_{{.*}} func
+; CHECK-NEXT: jb
+; CHECK-NEXT: call {{.*}} R_{{.*}} func
+; CHECK-OM1-LABEL: fcmpLe
+; CHECK-OM1: ucomiss
+; CHECK-OM1-NEXT: setb
+; CHECK-OM1: call {{.*}} R_{{.*}} func
+; CHECK-OM1: ucomisd
+; CHECK-OM1-NEXT: setb
+; CHECK-OM1: call {{.*}} R_{{.*}} func
 ; ARM32-LABEL: fcmpLe
 ; ARM32: vcmp.f32
 ; ARM32: vmrs
 ; ARM32-OM1: movls [[R0:r[0-9]+]], #0
 ; ARM32-OM1: movhi [[R0]], #1
 ; ARM32-O2: bhi
 ; ARM32: vcmp.f64
 ; ARM32: vmrs
 ; ARM32-OM1: movls [[R1:r[0-9]+]], #0
 ; ARM32-OM1: movhi [[R1]], #1
@@ skipping 495 matching lines @@
 }
 ; CHECK-LABEL: selectDoubleVarVar
 ; CHECK: ucomisd
 ; CHECK: seta
 ; CHECK: fld
 ; ARM32-LABEL: selectDoubleVarVar
 ; ARM32: vcmp.f64
 ; ARM32-OM1: vmovne.f64 d{{[0-9]+}}
 ; ARM32-O2: vmovmi.f64 d{{[0-9]+}}
 ; ARM32: bx