Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(41)

Side by Side Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 1435603003: Implemented the RoundInt64ToFloat32 TurboFan operator for x64, arm64, and mips64. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 1 month ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
OLDNEW
1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 56 matching lines...) Expand 10 before | Expand all | Expand 10 after
67 V(Mips64MaxD) \ 67 V(Mips64MaxD) \
68 V(Mips64MinD) \ 68 V(Mips64MinD) \
69 V(Mips64Float64RoundDown) \ 69 V(Mips64Float64RoundDown) \
70 V(Mips64Float64RoundTruncate) \ 70 V(Mips64Float64RoundTruncate) \
71 V(Mips64Float64RoundUp) \ 71 V(Mips64Float64RoundUp) \
72 V(Mips64CvtSD) \ 72 V(Mips64CvtSD) \
73 V(Mips64CvtDS) \ 73 V(Mips64CvtDS) \
74 V(Mips64TruncWD) \ 74 V(Mips64TruncWD) \
75 V(Mips64TruncUwD) \ 75 V(Mips64TruncUwD) \
76 V(Mips64CvtDW) \ 76 V(Mips64CvtDW) \
77 V(Mips64CvtSL) \
77 V(Mips64CvtDL) \ 78 V(Mips64CvtDL) \
78 V(Mips64CvtDUw) \ 79 V(Mips64CvtDUw) \
79 V(Mips64Lb) \ 80 V(Mips64Lb) \
80 V(Mips64Lbu) \ 81 V(Mips64Lbu) \
81 V(Mips64Sb) \ 82 V(Mips64Sb) \
82 V(Mips64Lh) \ 83 V(Mips64Lh) \
83 V(Mips64Lhu) \ 84 V(Mips64Lhu) \
84 V(Mips64Sh) \ 85 V(Mips64Sh) \
85 V(Mips64Ld) \ 86 V(Mips64Ld) \
86 V(Mips64Lw) \ 87 V(Mips64Lw) \
(...skipping 36 matching lines...) Expand 10 before | Expand all | Expand 10 after
123 #define TARGET_ADDRESSING_MODE_LIST(V) \ 124 #define TARGET_ADDRESSING_MODE_LIST(V) \
124 V(MRI) /* [%r0 + K] */ \ 125 V(MRI) /* [%r0 + K] */ \
125 V(MRR) /* [%r0 + %r1] */ 126 V(MRR) /* [%r0 + %r1] */
126 127
127 128
128 } // namespace compiler 129 } // namespace compiler
129 } // namespace internal 130 } // namespace internal
130 } // namespace v8 131 } // namespace v8
131 132
132 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 133 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
OLDNEW
« no previous file with comments | « src/compiler/mips64/code-generator-mips64.cc ('k') | src/compiler/mips64/instruction-selector-mips64.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698