Merge fixed alloca stack adjustments into the prolog

src/IceInst.cpp

 //===- subzero/src/IceInst.cpp - High-level instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 200 matching lines @@
           // vector. Instead, livenessPostprocess() verifies this after the
           // vector has been sorted.
           LiveEnd->push_back(std::make_pair(VarNum, InstNumber));
         }
       }
     }
   }
   return true;
 }
 
-InstAlloca::InstAlloca(Cfg *Func, Operand *ByteCount, uint32_t AlignInBytes,
-                       Variable *Dest)
+InstAlloca::InstAlloca(Cfg *Func, Variable *Dest, Operand *ByteCount,
+                       uint32_t AlignInBytes)
     : InstHighLevel(Func, Inst::Alloca, 1, Dest), AlignInBytes(AlignInBytes) {
   // Verify AlignInBytes is 0 or a power of 2.
   assert(AlignInBytes == 0 || llvm::isPowerOf2_32(AlignInBytes));
   addSource(ByteCount);
 }
 
 InstArithmetic::InstArithmetic(Cfg *Func, OpKind Op, Variable *Dest,
                                Operand *Source1, Operand *Source2)
     : InstHighLevel(Func, Inst::Arithmetic, 2, Dest), Op(Op) {
   addSource(Source1);
@@ skipping 723 matching lines @@
     // upper 32 bits of rax. We need to recognize and preserve these.
     return true;
   }
   if (!Dest->hasReg() && !SrcVar->hasReg() &&
       Dest->getStackOffset() == SrcVar->getStackOffset())
     return true;
   return false;
 }
 
 } // end of namespace Ice