MIPS: Use BOVC/BNVC for overflow checking on r6.

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 54bb55a146085cfca2baaecc3d1007aff64add97..b3af1a9d8ae95dbd9194a9c581423b870fa9bdd2 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -584,8 +584,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
       __ Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       break;
     case kMipsAddOvf:
-      __ AdduAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0),
-                                 i.InputOperand(1), kCompareReg, kScratchReg);
+      // Noop, AdduAndCheckForOverflow() executed at branch/result processing.

[paul.l..., 2015/11/13 02:16:20]

Other similar opcodes use:
// Pseudo-instruction used for tst/branch. No opcode emitted here.
// Pseudo-instruction used for cmp/branch. No opcode emitted here.
... etc.

[balazs.kilvady, 2015/11/20 19:28:08]

Done.

       break;
     case kMipsSub:
       __ Subu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
@@ -1036,9 +1035,22 @@ void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
     cc = FlagsConditionToConditionTst(branch->condition);
     __ And(at, i.InputRegister(0), i.InputOperand(1));
     __ Branch(tlabel, cc, at, Operand(zero_reg));
-  } else if (instr->arch_opcode() == kMipsAddOvf ||
-             instr->arch_opcode() == kMipsSubOvf) {
-    // kMipsAddOvf, SubOvf emit negative result to 'kCompareReg' on overflow.
+  } else if (instr->arch_opcode() == kMipsAddOvf) {
+    switch (branch->condition) {
+      case kOverflow:
+        __ AdduAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0),
+                                   i.InputOperand(1), tlabel, flabel);
+        break;
+      case kNotOverflow:
+        __ AdduAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0),
+                                   i.InputOperand(1), flabel, tlabel);
+        break;
+      default:
+        UNSUPPORTED_COND(kMipsAddOvf, branch->condition);
+        break;
+    }
+  } else if (instr->arch_opcode() == kMipsSubOvf) {
+    // kMipsSubOvf emit negative result to 'kCompareReg' on overflow.
     cc = FlagsConditionToConditionOvf(branch->condition);
     __ Branch(tlabel, cc, kCompareReg, Operand(zero_reg));
   } else if (instr->arch_opcode() == kMipsCmp) {
@@ -1105,8 +1117,16 @@ void CodeGenerator::AssembleArchBoolean(Instruction* instr,
       __ xori(result, result, 1);
     }
     return;
-  } else if (instr->arch_opcode() == kMipsAddOvf ||
-             instr->arch_opcode() == kMipsSubOvf) {
+  } else if (instr->arch_opcode() == kMipsAddOvf) {
+    Label flabel, tlabel;
+    __ AdduAndCheckForOverflow(i.OutputRegister(), i.InputRegister(0),
+                               i.InputOperand(1), nullptr, &flabel);
+    __ li(result, 1);

[Alan Li, 2015/11/20 01:28:39]

So I guess another very easy way to detect unsigned overflow addition and set
the result bit is like this:

Consider two unsigned 32bit values A, and B, and we do an unsigned add on both,
resulting value C. then C value is:

C = A + B

And the actual value C' that will be stored in the register is:

C' = (A + B) mod 2 ^32, which is: C' + 2^32 = A + B, since we know C' is greater
than 2^32

since that both A and B are less than 2^32, we will have:

C' + 2^32 = A + B < A + 2^32

So we will have the following:

C' < A and C' < B

So the easiest way to test whether there is an overflow, is to see if the
unsigned result C' is less than either operand A and B.

So we might be able to shrink the whole AdduAndCheckForOverflow, to be:

Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1))
sltu(result, i.OutputRegister(), i.OutputRegister())

[balazs.kilvady, 2015/11/20 19:28:08]

i.OutputRegister() is never (unsigned) less then itself so result is always zero
in sltu(result, i.OutputRegister(), i.OutputRegister());

I think if we compare with both operands then got something like
sltu(result, i.OutputRegister(), i.InputRegister(0));
Branch(&no_overflow , ne, result, zero_reg);
sltu(result, i.OutputRegister(), i.InputRegister(1));
Branch(&no_overflow , ne, result, zero_reg);

So we would have more instructions than currently.
And addu performs signed addition on MIPS.

But please do a followup CL and if that performs well then you can replace those
codes with your CL. But also do that CL following the final version of this one
(hopefully I upload that today) beacuse add/subOverflow functions will be
slighly changed.

Also please put these ideas to the github issue page or slack beacuse it is
easier to discuss ideas there.

+    __ Branch(&tlabel);
+    __ bind(&flabel);
+    __ li(result, 0);
+    __ bind(&tlabel);
+  } else if (instr->arch_opcode() == kMipsSubOvf) {
     // kMipsAddOvf, SubOvf emits negative result to 'kCompareReg' on overflow.
     cc = FlagsConditionToConditionOvf(condition);
     // Return 1 on overflow.