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Side by Side Diff: src/mips/assembler-mips.cc

Issue 1434263003: MIPS: Use BOVC/BNVC for overflow checking on r6. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rebase Created 5 years ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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1329 1329
1330 void Assembler::bne(Register rs, Register rt, int16_t offset) { 1330 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1331 BlockTrampolinePoolScope block_trampoline_pool(this); 1331 BlockTrampolinePoolScope block_trampoline_pool(this);
1332 GenInstrImmediate(BNE, rs, rt, offset); 1332 GenInstrImmediate(BNE, rs, rt, offset);
1333 BlockTrampolinePoolFor(1); // For associated delay slot. 1333 BlockTrampolinePoolFor(1); // For associated delay slot.
1334 } 1334 }
1335 1335
1336 1336
1337 void Assembler::bovc(Register rs, Register rt, int16_t offset) { 1337 void Assembler::bovc(Register rs, Register rt, int16_t offset) {
1338 DCHECK(IsMipsArchVariant(kMips32r6)); 1338 DCHECK(IsMipsArchVariant(kMips32r6));
1339 DCHECK(!(rs.is(zero_reg))); 1339 DCHECK(!rs.is(zero_reg));
1340 DCHECK(rs.code() >= rt.code()); 1340 if (rs.code() >= rt.code()) {
1341 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); 1341 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1342 } else {
1343 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1344 }
1342 } 1345 }
1343 1346
1344 1347
1345 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { 1348 void Assembler::bnvc(Register rs, Register rt, int16_t offset) {
1346 DCHECK(IsMipsArchVariant(kMips32r6)); 1349 DCHECK(IsMipsArchVariant(kMips32r6));
1347 DCHECK(!(rs.is(zero_reg))); 1350 DCHECK(!rs.is(zero_reg));
1348 DCHECK(rs.code() >= rt.code()); 1351 if (rs.code() >= rt.code()) {
1349 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); 1352 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH);
1353 } else {
1354 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH);
1355 }
1350 } 1356 }
1351 1357
1352 1358
1353 void Assembler::blezalc(Register rt, int16_t offset) { 1359 void Assembler::blezalc(Register rt, int16_t offset) {
1354 DCHECK(IsMipsArchVariant(kMips32r6)); 1360 DCHECK(IsMipsArchVariant(kMips32r6));
1355 DCHECK(!(rt.is(zero_reg))); 1361 DCHECK(!(rt.is(zero_reg)));
1356 positions_recorder()->WriteRecordedPositions(); 1362 positions_recorder()->WriteRecordedPositions();
1357 GenInstrImmediate(BLEZ, zero_reg, rt, offset, 1363 GenInstrImmediate(BLEZ, zero_reg, rt, offset,
1358 CompactBranchType::COMPACT_BRANCH); 1364 CompactBranchType::COMPACT_BRANCH);
1359 } 1365 }
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3047 3053
3048 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { 3054 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
3049 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); 3055 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t));
3050 } 3056 }
3051 } 3057 }
3052 3058
3053 } // namespace internal 3059 } // namespace internal
3054 } // namespace v8 3060 } // namespace v8
3055 3061
3056 #endif // V8_TARGET_ARCH_MIPS 3062 #endif // V8_TARGET_ARCH_MIPS
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