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| 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 // All Rights Reserved. | 2 // All Rights Reserved. |
| 3 // | 3 // |
| 4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
| 5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
| 6 // met: | 6 // met: |
| 7 // | 7 // |
| 8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
| 9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
| 10 // | 10 // |
| (...skipping 1317 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1328 | 1328 |
| 1329 void Assembler::bne(Register rs, Register rt, int16_t offset) { | 1329 void Assembler::bne(Register rs, Register rt, int16_t offset) { |
| 1330 BlockTrampolinePoolScope block_trampoline_pool(this); | 1330 BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1331 GenInstrImmediate(BNE, rs, rt, offset); | 1331 GenInstrImmediate(BNE, rs, rt, offset); |
| 1332 BlockTrampolinePoolFor(1); // For associated delay slot. | 1332 BlockTrampolinePoolFor(1); // For associated delay slot. |
| 1333 } | 1333 } |
| 1334 | 1334 |
| 1335 | 1335 |
| 1336 void Assembler::bovc(Register rs, Register rt, int16_t offset) { | 1336 void Assembler::bovc(Register rs, Register rt, int16_t offset) { |
| 1337 DCHECK(IsMipsArchVariant(kMips32r6)); | 1337 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1338 DCHECK(!(rs.is(zero_reg))); | 1338 DCHECK(!rs.is(zero_reg)); |
| 1339 DCHECK(rs.code() >= rt.code()); | 1339 if (rs.code() >= rt.code()) { |
| 1340 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); | 1340 GenInstrImmediate(ADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); |
| 1341 } else { |
| 1342 GenInstrImmediate(ADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); |
| 1343 } |
| 1341 } | 1344 } |
| 1342 | 1345 |
| 1343 | 1346 |
| 1344 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { | 1347 void Assembler::bnvc(Register rs, Register rt, int16_t offset) { |
| 1345 DCHECK(IsMipsArchVariant(kMips32r6)); | 1348 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1346 DCHECK(!(rs.is(zero_reg))); | 1349 DCHECK(!rs.is(zero_reg)); |
| 1347 DCHECK(rs.code() >= rt.code()); | 1350 if (rs.code() >= rt.code()) { |
| 1348 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); | 1351 GenInstrImmediate(DADDI, rs, rt, offset, CompactBranchType::COMPACT_BRANCH); |
| 1352 } else { |
| 1353 GenInstrImmediate(DADDI, rt, rs, offset, CompactBranchType::COMPACT_BRANCH); |
| 1354 } |
| 1349 } | 1355 } |
| 1350 | 1356 |
| 1351 | 1357 |
| 1352 void Assembler::blezalc(Register rt, int16_t offset) { | 1358 void Assembler::blezalc(Register rt, int16_t offset) { |
| 1353 DCHECK(IsMipsArchVariant(kMips32r6)); | 1359 DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1354 DCHECK(!(rt.is(zero_reg))); | 1360 DCHECK(!(rt.is(zero_reg))); |
| 1355 positions_recorder()->WriteRecordedPositions(); | 1361 positions_recorder()->WriteRecordedPositions(); |
| 1356 GenInstrImmediate(BLEZ, zero_reg, rt, offset, | 1362 GenInstrImmediate(BLEZ, zero_reg, rt, offset, |
| 1357 CompactBranchType::COMPACT_BRANCH); | 1363 CompactBranchType::COMPACT_BRANCH); |
| 1358 } | 1364 } |
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| 3023 | 3029 |
| 3024 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 3030 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
| 3025 CpuFeatures::FlushICache(pc, 2 * sizeof(int32_t)); | 3031 CpuFeatures::FlushICache(pc, 2 * sizeof(int32_t)); |
| 3026 } | 3032 } |
| 3027 } | 3033 } |
| 3028 | 3034 |
| 3029 } // namespace internal | 3035 } // namespace internal |
| 3030 } // namespace v8 | 3036 } // namespace v8 |
| 3031 | 3037 |
| 3032 #endif // V8_TARGET_ARCH_MIPS | 3038 #endif // V8_TARGET_ARCH_MIPS |
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