ARM Skia NEON patches - 35 - First AArch64 support

include/core/SkOnce.h

Index: include/core/SkOnce.h
diff --git a/include/core/SkOnce.h b/include/core/SkOnce.h
index daeb819d428408d36ef4cb7b72407d2a12fc01e9..d5330b94087a1d52e2ce8336747e0642075f8523 100644
--- a/include/core/SkOnce.h
+++ b/include/core/SkOnce.h
@@ -85,12 +85,10 @@ inline static void compiler_barrier() {
 #endif
 
 inline static void full_barrier_on_arm() {
-#ifdef SK_CPU_ARM
-#  if SK_ARM_ARCH >= 7
-    asm volatile("dmb" : : : "memory");
-#  else
+#if (defined(SK_CPU_ARM) && SK_ARM_ARCH >= 7) || defined(SK_CPU_ARM64)
+    asm volatile("dmb ish" : : : "memory");

[kevin.petit, 2014/03/24 11:42:08]

This barrier is less restrictive than the one previously used. If I've
understood things correctly, SkOnce is only used for synchronisation between
cores. This one line is not arm64-specific and you might want to see it as a
separate patch.

+#elif defined(SK_CPU_ARM)
     asm volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
-#  endif
 #endif
 }