ARM Skia NEON patches - 35 - First AArch64 support

include/core/SkOnce.h

 /*
  * Copyright 2013 Google Inc.
  *
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
 
 #ifndef SkOnce_DEFINED
 #define SkOnce_DEFINED
 
@@ skipping 43 matching lines @@
 inline static void compiler_barrier() {
     _ReadWriteBarrier();
 }
 #else
 inline static void compiler_barrier() {
     asm volatile("" : : : "memory");
 }
 #endif
 
 inline static void full_barrier_on_arm() {
-#ifdef SK_CPU_ARM
-#  if SK_ARM_ARCH >= 7
-    asm volatile("dmb" : : : "memory");
-#  else
+#if (defined(SK_CPU_ARM) && SK_ARM_ARCH >= 7) || defined(SK_CPU_ARM64)
+    asm volatile("dmb ish" : : : "memory");
+#elif defined(SK_CPU_ARM)
     asm volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory");
-#  endif
 #endif
 }
 
 // On every platform, we issue a compiler barrier to prevent it from reordering
 // code.  That's enough for platforms like x86 where release and acquire
 // barriers are no-ops.  On other platforms we may need to be more careful;
 // ARM, in particular, needs real code for both acquire and release.  We use a
 // full barrier, which acts as both, because that the finest precision ARM
 // provides.
 
@@ skipping 51 matching lines @@
     //
     // The release barrier in sk_once_slow guaranteed that once->done = true
     // happens after f(arg), so by syncing to once->done = true here we're
     // forcing ourselves to also wait until the effects of f(arg) are readble.
     acquire_barrier();
 }
 
 #undef SK_ANNOTATE_BENIGN_RACE
 
 #endif  // SkOnce_DEFINED