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Side by Side Diff: src/IceInstARM32.cpp

Issue 1433743002: Add POP instruction to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Merged into master Created 5 years, 1 month ago
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1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 1098 matching lines...) Expand 10 before | Expand all | Expand 10 after
1109 continue; 1109 continue;
1110 startNextInst(Func); 1110 startNextInst(Func);
1111 Str << "\t" 1111 Str << "\t"
1112 << "vpop" 1112 << "vpop"
1113 << "\t{"; 1113 << "\t{";
1114 Op->emit(Func); 1114 Op->emit(Func);
1115 Str << "}\n"; 1115 Str << "}\n";
1116 } 1116 }
1117 } 1117 }
1118 1118
1119 void InstARM32Pop::emitIAS(const Cfg *Func) const {
1120 SizeT IntegerCount = 0;
1121 ARM32::IValueT GPRegisters = 0;
1122 const Variable *LastDest = nullptr;
1123 for (const Variable *Var : Dests) {
1124 if (!isScalarIntegerType(Var->getType()))
1125 // TODO(kschimpf) Implement vpush.
1126 return emitUsingTextFixup(Func);
1127 assert((Var && Var->hasReg()) && "pop only applies to registers");
1128 int32_t Reg = Var->getRegNum();
1129 assert(Reg != RegARM32::Encoded_Not_GPR);
1130 LastDest = Var;
1131 GPRegisters |= (1 << Reg);
1132 ++IntegerCount;
1133 }
1134 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
1135 switch (IntegerCount) {
1136 case 0:
1137 return;
1138 case 1:
1139 // Note: Can only apply pop register if single register is not sp.
1140 assert((RegARM32::Encoded_Reg_sp != LastDest->getRegNum()) &&
1141 "Effects of pop register SP is undefined!");
1142 // TODO(kschimpf) ARM sandbox does not allow the single register form of
1143 // pop, and the popList form expects multiple registers. Convert this
1144 // assert to a conditional check once it has been shown that popList
1145 // works.
1146 assert(!Func->getContext()->getFlags().getUseSandboxing() &&
1147 "pop register not in ARM sandbox!");
1148 Asm->pop(LastDest, CondARM32::AL);
1149 break;
1150 default:
1151 Asm->popList(GPRegisters, CondARM32::AL);
1152 break;
1153 }
1154 if (Asm->needsTextFixup())
1155 emitUsingTextFixup(Func);
1156 }
1157
1119 void InstARM32Pop::dump(const Cfg *Func) const { 1158 void InstARM32Pop::dump(const Cfg *Func) const {
1120 if (!BuildDefs::dump()) 1159 if (!BuildDefs::dump())
1121 return; 1160 return;
1122 Ostream &Str = Func->getContext()->getStrDump(); 1161 Ostream &Str = Func->getContext()->getStrDump();
1123 Str << "pop" 1162 Str << "pop"
1124 << " "; 1163 << " ";
1125 for (SizeT I = 0; I < Dests.size(); ++I) { 1164 for (SizeT I = 0; I < Dests.size(); ++I) {
1126 if (I > 0) 1165 if (I > 0)
1127 Str << ", "; 1166 Str << ", ";
1128 Dests[I]->dump(Func); 1167 Dests[I]->dump(Func);
(...skipping 61 matching lines...) Expand 10 before | Expand all | Expand 10 after
1190 Str << ", "; 1229 Str << ", ";
1191 Op->emit(Func); 1230 Op->emit(Func);
1192 PrintComma = true; 1231 PrintComma = true;
1193 } 1232 }
1194 } 1233 }
1195 Str << "}\n"; 1234 Str << "}\n";
1196 } 1235 }
1197 } 1236 }
1198 1237
1199 void InstARM32Push::emitIAS(const Cfg *Func) const { 1238 void InstARM32Push::emitIAS(const Cfg *Func) const {
1200 SizeT SrcReg = 0;
1201 SizeT IntegerCount = 0; 1239 SizeT IntegerCount = 0;
1202 ARM32::IValueT GPURegisters = 0; 1240 ARM32::IValueT GPRegisters = 0;
1203 for (SizeT i = 0; i < getSrcSize(); ++i) { 1241 const Variable *LastSrc = nullptr;
1204 if (!isScalarIntegerType(getSrc(i)->getType())) 1242 for (SizeT Index = 0; Index < getSrcSize(); ++Index) {
1243 if (!isScalarIntegerType(getSrc(Index)->getType()))
1205 // TODO(kschimpf) Implement vpush. 1244 // TODO(kschimpf) Implement vpush.
1206 return emitUsingTextFixup(Func); 1245 return emitUsingTextFixup(Func);
1207 auto *Var = llvm::dyn_cast<Variable>(getSrc(i)); 1246 const auto *Var = llvm::dyn_cast<Variable>(getSrc(Index));
1208 assert((Var && Var->hasReg()) && "push only applies to registers"); 1247 assert((Var && Var->hasReg()) && "push only applies to registers");
1209 ARM32::IValueT Reg = Var->getRegNum(); 1248 int32_t Reg = Var->getRegNum();
1210 assert(Reg != static_cast<ARM32::IValueT>(RegARM32::Encoded_Not_GPR)); 1249 assert(Reg != RegARM32::Encoded_Not_GPR);
1211 SrcReg = i; 1250 LastSrc = Var;
1212 GPURegisters |= (1 << Reg); 1251 GPRegisters |= (1 << Reg);
1213 ++IntegerCount; 1252 ++IntegerCount;
1214 } 1253 }
1215 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>(); 1254 auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
1216 switch (IntegerCount) { 1255 switch (IntegerCount) {
1217 case 0: 1256 case 0:
1218 return; 1257 return;
1219 case 1: { 1258 case 1: {
1220 if (auto *Var = llvm::dyn_cast<Variable>(getSrc(SrcReg))) { 1259 // Note: Can only apply push register if single register is not sp.
1221 // Note: Can only apply push register if single register is not sp. 1260 assert((RegARM32::Encoded_Reg_sp != LastSrc->getRegNum()) &&
1222 assert((RegARM32::Encoded_Reg_sp != Var->getRegNum()) && 1261 "Effects of push register SP is undefined!");
1223 "Effects of push register SP is undefined!"); 1262 // TODO(kschimpf) ARM sandbox does not allow the single register form of
1224 // TODO(kschimpf) ARM sandbox does not allow the single register form of 1263 // push, and the pushList form expects multiple registers. Convert this
1225 // push, and the pushList form expects multiple registers. Convert this 1264 // assert to a conditional check once it has been shown that pushList
1226 // assert to a conditional check once it has been shown that pushList 1265 // works.
1227 // works. 1266 assert(!Func->getContext()->getFlags().getUseSandboxing() &&
1228 assert(!Func->getContext()->getFlags().getUseSandboxing() && 1267 "push register not in ARM sandbox!");
1229 "push register not in ARM sandbox!"); 1268 Asm->push(LastSrc, CondARM32::AL);
1230 Asm->push(Var, CondARM32::AL); 1269 break;
1231 break;
1232 }
1233 // Intentionally fall to next case.
1234 } 1270 }
1235 default: 1271 default:
1236 // TODO(kschimpf) Implement pushList in assembler. 1272 // TODO(kschimpf) Implement pushList in assembler.
1237 Asm->pushList(GPURegisters, CondARM32::AL); 1273 Asm->pushList(GPRegisters, CondARM32::AL);
1238 break; 1274 break;
1239 } 1275 }
1240 if (Asm->needsTextFixup()) 1276 if (Asm->needsTextFixup())
1241 emitUsingTextFixup(Func); 1277 emitUsingTextFixup(Func);
1242 } 1278 }
1243 1279
1244 void InstARM32Push::dump(const Cfg *Func) const { 1280 void InstARM32Push::dump(const Cfg *Func) const {
1245 if (!BuildDefs::dump()) 1281 if (!BuildDefs::dump())
1246 return; 1282 return;
1247 Ostream &Str = Func->getContext()->getStrDump(); 1283 Ostream &Str = Func->getContext()->getStrDump();
(...skipping 454 matching lines...) Expand 10 before | Expand all | Expand 10 after
1702 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>; 1738 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
1703 template class InstARM32UnaryopFP<InstARM32::Vsqrt>; 1739 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
1704 1740
1705 template class InstARM32FourAddrGPR<InstARM32::Mla>; 1741 template class InstARM32FourAddrGPR<InstARM32::Mla>;
1706 template class InstARM32FourAddrGPR<InstARM32::Mls>; 1742 template class InstARM32FourAddrGPR<InstARM32::Mls>;
1707 1743
1708 template class InstARM32CmpLike<InstARM32::Cmp>; 1744 template class InstARM32CmpLike<InstARM32::Cmp>;
1709 template class InstARM32CmpLike<InstARM32::Tst>; 1745 template class InstARM32CmpLike<InstARM32::Tst>;
1710 1746
1711 } // end of namespace Ice 1747 } // end of namespace Ice
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