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Issue 1433743002: Add POP instruction to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Merged into master Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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182 182
183 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm, 183 void mla(const Operand *OpRd, const Operand *OpRn, const Operand *OpRm,
184 const Operand *OpRa, CondARM32::Cond Cond); 184 const Operand *OpRa, CondARM32::Cond Cond);
185 185
186 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 186 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
187 bool SetFlags, CondARM32::Cond Cond); 187 bool SetFlags, CondARM32::Cond Cond);
188 188
189 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 189 void orr(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
190 bool SetFlags, CondARM32::Cond Cond); 190 bool SetFlags, CondARM32::Cond Cond);
191 191
192 void pop(const Operand *OpRt, CondARM32::Cond Cond);
193
194 // Note: Registers is a bitset, where bit n corresponds to register Rn.
195 void popList(const IValueT Registers, CondARM32::Cond Cond);
196
192 void push(const Operand *OpRt, CondARM32::Cond Cond); 197 void push(const Operand *OpRt, CondARM32::Cond Cond);
193 198
194 // Note: Registers is a bitset, where bit n corresponds to register Rn. 199 // Note: Registers is a bitset, where bit n corresponds to register Rn.
195 void pushList(const IValueT Registers, CondARM32::Cond Cond); 200 void pushList(const IValueT Registers, CondARM32::Cond Cond);
196 201
197 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 202 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
198 bool SetFlags, CondARM32::Cond Cond); 203 bool SetFlags, CondARM32::Cond Cond);
199 204
200 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, 205 void sdiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
201 CondARM32::Cond Cond); 206 CondARM32::Cond Cond);
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308 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); 313 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
309 314
310 // Returns the offset encoded in the branch instruction Inst. 315 // Returns the offset encoded in the branch instruction Inst.
311 static IOffsetT decodeBranchOffset(IValueT Inst); 316 static IOffsetT decodeBranchOffset(IValueT Inst);
312 }; 317 };
313 318
314 } // end of namespace ARM32 319 } // end of namespace ARM32
315 } // end of namespace Ice 320 } // end of namespace Ice
316 321
317 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H 322 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H
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