Add POP instruction to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 888 matching lines @@
   //
   // ORR (register) - ARM Section A8.8.123, encoding A1:
   //   orr{s}<c> <Rd>, <Rn>,  #<RotatedImm8>
   //
   // cccc0001100snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
   // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8.
   constexpr IValueT Orr = B3 | B2; // i.e. 1100
   emitType01(Orr, OpRd, OpRn, OpSrc1, SetFlags, Cond);
 }
 
+void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
+  // POP - ARM section A8.8.132, encoding A2:
+  //   pop<c> {Rt}
+  //
+  // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
+  IValueT Rt;
+  if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  assert(Rt != RegARM32::Encoded_Reg_sp);
+  // Same as load instruction.
+  constexpr bool IsLoad = true;
+  constexpr bool IsByte = false;
+  IValueT Address = decodeImmRegOffset(RegARM32::Encoded_Reg_sp, kWordSize,
+                                       OperandARM32Mem::PostIndex);
+  emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
+}
+
+void AssemblerARM32::popList(const IValueT Registers, CondARM32::Cond Cond) {
+  // POP - ARM section A8.*.131, encoding A1:
+  //   pop<c> <registers>
+  //
+  // cccc100010111101rrrrrrrrrrrrrrrr where cccc=Cond and
+  // rrrrrrrrrrrrrrrr=Registers (one bit for each GP register).
+  constexpr bool IsLoad = true;
+  emitMultiMemOp(Cond, IA_W, IsLoad, RegARM32::Encoded_Reg_sp, Registers);
+}
+
 void AssemblerARM32::push(const Operand *OpRt, CondARM32::Cond Cond) {
   // PUSH - ARM section A8.8.133, encoding A2:
   //   push<c> {Rt}
   //
-  // cccc010100101101dddd000000000100 where dddd=Rd and cccc=Cond.
+  // cccc010100101101dddd000000000100 where dddd=Rt and cccc=Cond.
   IValueT Rt;
   if (decodeOperand(OpRt, Rt) != DecodedAsRegister)
     return setNeedsTextFixup();
   assert(Rt != RegARM32::Encoded_Reg_sp);
   // Same as store instruction.
   constexpr bool isLoad = false;
   constexpr bool isByte = false;
   IValueT Address = decodeImmRegOffset(RegARM32::Encoded_Reg_sp, -kWordSize,
                                        OperandARM32Mem::PreIndex);
   emitMemOp(Cond, kInstTypeMemImmediate, isLoad, isByte, Rt, Address);
@@ skipping 146 matching lines @@
   if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
       Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
       RdHi == RdLo)
     llvm::report_fatal_error("Umull instruction unpredictable on pc");
   constexpr bool SetFlags = false;
   emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice