Add POP instruction to ARM integrated assembler.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1098 matching lines @@
       continue;
     startNextInst(Func);
     Str << "\t"
         << "vpop"
         << "\t{";
     Op->emit(Func);
     Str << "}\n";
   }
 }
 
+void InstARM32Pop::emitIAS(const Cfg *Func) const {
+  SizeT DestReg = 0;
+  SizeT IntegerCount = 0;
+  ARM32::IValueT GPRegisters = 0;
+  for (SizeT i = 0; i < Dests.size(); ++i) {

[Jim Stichnoth, 2015/11/09 22:17:26]

Consider using a range-based for loop:

  Variable *LastDest = nullptr; // replaces DestReg
  for (Variable *Var : Dests) {
    ...
    LastDest = Var; // replaces DestReg=i;
  }

+    Operand *Op = Dests[i];
+    if (!isScalarIntegerType(Op->getType()))
+      // TODO(kschimpf) Implement vpush.
+      return emitUsingTextFixup(Func);
+    auto *Var = llvm::dyn_cast<Variable>(Op);
+    assert((Var && Var->hasReg()) && "pop only applies to registers");
+    ARM32::IValueT Reg = Var->getRegNum();

[Jim Stichnoth, 2015/11/09 22:17:26]

I think you're better off declaring this as int32_t.

[Karl, 2015/11/09 22:44:35]

Forgot that Encoded_Not_GPR is negative. Changing.

+    assert(Reg != static_cast<ARM32::IValueT>(RegARM32::Encoded_Not_GPR));
+    DestReg = i;
+    GPRegisters |= (1 << Reg);
+    ++IntegerCount;
+  }
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  switch (IntegerCount) {
+  case 0:
+    return;
+  case 1: {
+    if (auto *Var = llvm::dyn_cast<Variable>(Dests[DestReg])) {

[Jim Stichnoth, 2015/11/09 22:17:26]

Dests[] is a VarList, so the dyn_cast is unnecessary.

[Karl, 2015/11/09 22:44:35]

Done.

+      // Note: Can only apply pop register if single register is not sp.
+      assert((RegARM32::Encoded_Reg_sp != Var->getRegNum()) &&
+             "Effects of pop register SP is undefined!");
+      // TODO(kschimpf) ARM sandbox does not allow the single register form of
+      // pop, and the popList form expects multiple registers. Convert this
+      // assert to a conditional check once it has been shown that popList
+      // works.
+      assert(!Func->getContext()->getFlags().getUseSandboxing() &&
+             "pop register not in ARM sandbox!");
+      Asm->pop(Var, CondARM32::AL);
+      break;
+    }
+    // Intentionally fall to next case.
+  }
+  default:
+    Asm->popList(GPURegisters, CondARM32::AL);

[Jim Stichnoth, 2015/11/09 22:17:26]

GPURegisters?  Should this be GPRegisters?

+    break;
+  }
+  if (Asm->needsTextFixup())
+    emitUsingTextFixup(Func);
+}
+
 void InstARM32Pop::dump(const Cfg *Func) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "pop"
       << " ";
   for (SizeT I = 0; I < Dests.size(); ++I) {
     if (I > 0)
       Str << ", ";
     Dests[I]->dump(Func);
@@ skipping 573 matching lines @@
 template class InstARM32UnaryopGPR<InstARM32::Uxt, true>;
 template class InstARM32UnaryopFP<InstARM32::Vsqrt>;
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace Ice