[machine-operator-reducer] fix float truncation

src/compiler/arm64/instruction-selector-arm64.cc

Index: src/compiler/arm64/instruction-selector-arm64.cc
diff --git a/src/compiler/arm64/instruction-selector-arm64.cc b/src/compiler/arm64/instruction-selector-arm64.cc
index 3149566a56f8fafd632c75ef29a55941e666fcee..45ce9175362e52139828867cacf15cca683268fd 100644
--- a/src/compiler/arm64/instruction-selector-arm64.cc
+++ b/src/compiler/arm64/instruction-selector-arm64.cc
@@ -148,17 +148,23 @@ bool TryMatchAnyShift(InstructionSelector* selector, Node* node,
   if (input_node->InputCount() != 2) return false;
   if (!g.IsIntegerConstant(input_node->InputAt(1))) return false;
 
+  // Shift right can't be grouped with 32-bit operation, because the data
+  // will be lost.
+  bool is_word_output = !IrOpcode::Is64(node->opcode());

[titzer, 2015/11/13 23:35:17]

Can you move this condition inline (so that it is not evaluated for every case)?

[fedor.indutny, 2015/11/14 00:15:52]

Acknowledged.

+
   switch (input_node->opcode()) {
     case IrOpcode::kWord32Shl:
     case IrOpcode::kWord64Shl:
       *opcode |= AddressingModeField::encode(kMode_Operand2_R_LSL_I);
       return true;
-    case IrOpcode::kWord32Shr:
     case IrOpcode::kWord64Shr:
+      if (is_word_output) return false;
+    case IrOpcode::kWord32Shr:
       *opcode |= AddressingModeField::encode(kMode_Operand2_R_LSR_I);
       return true;
-    case IrOpcode::kWord32Sar:
     case IrOpcode::kWord64Sar:
+      if (is_word_output) return false;
+    case IrOpcode::kWord32Sar:
       *opcode |= AddressingModeField::encode(kMode_Operand2_R_ASR_I);
       return true;
     case IrOpcode::kWord32Ror: