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Side by Side Diff: src/IceAssemblerARM32.cpp

Issue 1432453003: Fix base register for stack variables in ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix minor mistake Created 5 years, 1 month ago
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1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===// 1 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
2 // 2 //
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
4 // for details. All rights reserved. Use of this source code is governed by a 4 // for details. All rights reserved. Use of this source code is governed by a
5 // BSD-style license that can be found in the LICENSE file. 5 // BSD-style license that can be found in the LICENSE file.
6 // 6 //
7 // Modified by the Subzero authors. 7 // Modified by the Subzero authors.
8 // 8 //
9 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===//
10 // 10 //
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229 // Decodes memory address Opnd, and encodes that information into Value, 229 // Decodes memory address Opnd, and encodes that information into Value,
230 // based on how ARM represents the address. Returns how the value was encoded. 230 // based on how ARM represents the address. Returns how the value was encoded.
231 DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value) { 231 DecodedResult decodeAddress(const Operand *Opnd, IValueT &Value) {
232 if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) { 232 if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
233 // Should be a stack variable, with an offset. 233 // Should be a stack variable, with an offset.
234 if (Var->hasReg()) 234 if (Var->hasReg())
235 return CantDecode; 235 return CantDecode;
236 const IOffsetT Offset = Var->getStackOffset(); 236 const IOffsetT Offset = Var->getStackOffset();
237 if (!Utils::IsAbsoluteUint(12, Offset)) 237 if (!Utils::IsAbsoluteUint(12, Offset))
238 return CantDecode; 238 return CantDecode;
239 Value = decodeImmRegOffset(RegARM32::Encoded_Reg_sp, Offset, 239 RegARM32::GPRRegister BaseReg = RegARM32::Encoded_Reg_sp;
240 OperandARM32Mem::Offset); 240 if (const auto *StackVar = llvm::dyn_cast<StackVariable>(Var))
241 BaseReg = decodeGPRRegister(StackVar->getBaseRegNum());
242 Value = decodeImmRegOffset(BaseReg, Offset, OperandARM32Mem::Offset);
241 return DecodedAsImmRegOffset; 243 return DecodedAsImmRegOffset;
242 } 244 }
243 if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) { 245 if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
244 if (Mem->isRegReg()) 246 if (Mem->isRegReg())
245 // TODO(kschimpf) Add this case. 247 // TODO(kschimpf) Add this case.
246 return CantDecode; 248 return CantDecode;
247 Variable *Var = Mem->getBase(); 249 Variable *Var = Mem->getBase();
248 if (!Var->hasReg()) 250 if (!Var->hasReg())
249 return CantDecode; 251 return CantDecode;
250 ConstantInteger32 *Offset = Mem->getOffset(); 252 ConstantInteger32 *Offset = Mem->getOffset();
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980 // sub{s}<c> sp, <Rn>, #<RotatedImm8> 982 // sub{s}<c> sp, <Rn>, #<RotatedImm8>
981 // 983 //
982 // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn, 984 // cccc0010010snnnnddddiiiiiiiiiiii where cccc=Cond, dddd=Rd, nnnn=Rn,
983 // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8 985 // s=SetFlags and iiiiiiiiiiii=Src1Value defining RotatedImm8
984 constexpr IValueT Sub = B1; // 0010 986 constexpr IValueT Sub = B1; // 0010
985 emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond); 987 emitType01(Sub, OpRd, OpRn, OpSrc1, SetFlags, Cond);
986 } 988 }
987 989
988 } // end of namespace ARM32 990 } // end of namespace ARM32
989 } // end of namespace Ice 991 } // end of namespace Ice
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