Implement UXTB and UXTH in the ARM integerated assembler.

src/IceAssemblerARM32.h

Index: src/IceAssemblerARM32.h
diff --git a/src/IceAssemblerARM32.h b/src/IceAssemblerARM32.h
index e40e359d329cc816220f81394302af645aee1771..e524e4224fe0a346141cac3197e543eb066f4bc7 100644
--- a/src/IceAssemblerARM32.h
+++ b/src/IceAssemblerARM32.h
@@ -59,6 +59,14 @@ class AssemblerARM32 : public Assembler {
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
+  // Rotation values.
+  enum RotationValue {
+    kRotateNone, // Omitted
+    kRotate8,    // ror #8
+    kRotate16,   // ror #16
+    kRotate24    // ror #24
+  };
+
   class TargetInfo {
     TargetInfo(const TargetInfo &) = delete;
     TargetInfo &operator=(const TargetInfo &) = delete;
@@ -250,6 +258,9 @@ public:
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
+  // Implements uxtb/uxth depending on type of OpSrc0.
+  void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
+
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
@@ -333,6 +344,12 @@ private:
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetCc);
 
+  // Implements various forms of Unsigned extend value, using pattern
+  // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
+  // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
+  void emitUxt(CondARM32::Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
+               IValueT Rm, RotationValue Rotation);
+
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.