Implement UXTB and UXTH in the ARM integerated assembler.

src/IceAssemblerARM32.h

 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 41 matching lines @@
 public:
   MoveRelocatableFixup() = default;
   size_t emit(GlobalContext *Ctx, const Assembler &Asm) const override;
 };
 
 class AssemblerARM32 : public Assembler {
   AssemblerARM32(const AssemblerARM32 &) = delete;
   AssemblerARM32 &operator=(const AssemblerARM32 &) = delete;
 
 public:
+  // Rotation values.
+  enum RotationValue {
+    kRotateNone, // Omitted
+    kRotate8,    // ror #8
+    kRotate16,   // ror #16
+    kRotate24    // ror #24
+  };
+
   class TargetInfo {
     TargetInfo(const TargetInfo &) = delete;
     TargetInfo &operator=(const TargetInfo &) = delete;
 
   public:
     TargetInfo(bool HasFramePointer, SizeT FrameOrStackReg,
                int32_t StackAdjustment)
         : HasFramePointer(HasFramePointer), FrameOrStackReg(FrameOrStackReg),
           StackAdjustment(StackAdjustment) {}
     explicit TargetInfo(const TargetLowering *Target)
@@ skipping 171 matching lines @@
            bool SetFlags, CondARM32::Cond Cond);
 
   void tst(const Operand *OpRn, const Operand *OpSrc1, CondARM32::Cond Cond);
 
   void udiv(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1,
             CondARM32::Cond Cond);
 
   void umull(const Operand *OpRdLo, const Operand *OpRdHi, const Operand *OpRn,
              const Operand *OpRm, CondARM32::Cond Cond);
 
+  // Implements uxtb/uxth depending on type of OpSrc0.
+  void uxt(const Operand *OpRd, const Operand *OpSrc0, CondARM32::Cond Cond);
+
   static bool classof(const Assembler *Asm) {
     return Asm->getKind() == Asm_ARM32;
   }
 
   void emitTextInst(const std::string &Text, SizeT InstSize);
 
 private:
   // A vector of pool-allocated x86 labels for CFG nodes.
   using LabelVector = std::vector<Label *>;
   LabelVector CfgNodeLabels;
@@ skipping 63 matching lines @@
   // Pattern cccc011100x1dddd1111mmmm0001nnn where cccc=Cond,
   // x=Opcode, dddd=Rd, nnnn=Rn, mmmm=Rm.
   void emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm);
 
   // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn,
   // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode.
   void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
                  IValueT Rm, IValueT Rs, bool SetCc);
 
+  // Implements various forms of Unsigned extend value, using pattern
+  // ccccxxxxxxxxnnnnddddrr000111mmmm where cccc=Cond, xxxxxxxx<<20=Opcode,
+  // nnnn=Rn, dddd=Rd, rr=Rotation, and mmmm=Rm.
+  void emitUxt(CondARM32::Cond, IValueT Opcode, IValueT Rd, IValueT Rn,
+               IValueT Rm, RotationValue Rotation);
+
   // Pattern cccctttxxxxnnnn0000iiiiiiiiiiii where cccc=Cond, nnnn=Rn,
   // ttt=Instruction type (derived from OpSrc1), iiiiiiiiiiii is derived from
   // OpSrc1, and xxxx=Opcode.
   void emitCompareOp(IValueT Opcode, const Operand *OpRn, const Operand *OpSrc1,
                      CondARM32::Cond Cond);
 
   void emitBranch(Label *L, CondARM32::Cond, bool Link);
 
   // Encodes the given Offset into the branch instruction Inst.
   IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst);
 
   // Returns the offset encoded in the branch instruction Inst.
   static IOffsetT decodeBranchOffset(IValueT Inst);
 
   // Implements movw, generating pattern ccccxxxxxxxsiiiiddddiiiiiiiiiiii where
   // cccc=Cond, xxxxxxx<<21=Opcode, dddd=Rd, s=SetFlags, and
   // iiiiiiiiiiiiiiii=Imm16.
   void emitMovw(IValueT Opcode, IValueT Rd, IValueT Imm16, bool SetFlags,
                 CondARM32::Cond Cond);
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H