Implement UXTB and UXTH in the ARM integerated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 72 matching lines @@
 static constexpr IValueT kRotateShift = 8;
 
 // Shift instruction register fields encodings.
 static constexpr IValueT kShiftImmShift = 7;
 static constexpr IValueT kShiftImmBits = 5;
 static constexpr IValueT kShiftShift = 5;
 
 static constexpr IValueT kImmed12Bits = 12;
 static constexpr IValueT kImm12Shift = 0;
 
+// Rotation instructions (uxtb etc.).
+static constexpr IValueT kRotationShift = 10;
+
 // Div instruction register field encodings.
 static constexpr IValueT kDivRdShift = 16;
 static constexpr IValueT kDivRmShift = 8;
 static constexpr IValueT kDivRnShift = 0;
 
 // Type of instruction encoding (bits 25-27). See ARM section A5.1
 static constexpr IValueT kInstTypeDataRegister = 0;  // i.e. 000
 static constexpr IValueT kInstTypeDataImmediate = 1; // i.e. 001
 static constexpr IValueT kInstTypeMemImmediate = 2;  // i.e. 010
 
 // Offset modifier to current PC for next instruction.  The offset is off by 8
 // due to the way the ARM CPUs read PC.
 static constexpr IOffsetT kPCReadOffset = 8;
 
 // Mask to pull out PC offset from branch (b) instruction.
 static constexpr int kBranchOffsetBits = 24;
 static constexpr IOffsetT kBranchOffsetMask = 0x00ffffff;
 
 inline IValueT encodeBool(bool B) { return B ? 1 : 0; }
 
+inline IValueT encodeRotation(ARM32::AssemblerARM32::RotationValue Value) {
+  return static_cast<IValueT>(Value);
+}
+
 inline IValueT encodeGPRRegister(RegARM32::GPRRegister Rn) {
   return static_cast<IValueT>(Rn);
 }
 
 inline RegARM32::GPRRegister decodeGPRRegister(IValueT R) {
   return static_cast<RegARM32::GPRRegister>(R);
 }
 
 inline bool isGPRRegisterDefined(RegARM32::GPRRegister R) {
   return R != RegARM32::Encoded_Not_GPR;
@@ skipping 415 matching lines @@
       !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
                      (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
                      (Rd << kRdShift) | (Rs << kRsShift) | B7 | B4 |
                      (Rm << kRmShift);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitUxt(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
+                             IValueT Rn, IValueT Rm, RotationValue Rotation) {
+  IValueT Rot = encodeRotation(Rotation);
+  if (!isConditionDefined(Cond) || !Utils::IsUint(2, Rot))
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
+                     (Rn << kRnShift) | (Rd << kRdShift) |
+                     (Rot << kRotationShift) | B6 | B5 | B4 | (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::emitMultiMemOp(CondARM32::Cond Cond,
                                     BlockAddressMode AddressMode, bool IsLoad,
                                     IValueT BaseReg, IValueT Registers) {
   constexpr IValueT NumGPRegisters = 16;
   if (!isConditionDefined(Cond) || !isGPRRegisterDefined(BaseReg) ||
       Registers >= (1 << NumGPRegisters))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 |
                      AddressMode | (IsLoad ? L : 0) | (BaseReg << kRnShift) |
@@ skipping 566 matching lines @@
       decodeOperand(OpRm, Rm) != DecodedAsRegister)
     return setNeedsTextFixup();
   if (RdHi == RegARM32::Encoded_Reg_pc || RdLo == RegARM32::Encoded_Reg_pc ||
       Rn == RegARM32::Encoded_Reg_pc || Rm == RegARM32::Encoded_Reg_pc ||
       RdHi == RdLo)
     llvm::report_fatal_error("Umull instruction unpredictable on pc");
   constexpr bool SetFlags = false;
   emitMulOp(Cond, B23, RdLo, RdHi, Rn, Rm, SetFlags);
 }
 
+void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
+                         CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // Note: For the moment, we assume no rotation is specified.
+  RotationValue Rotation = kRotateNone;
+  constexpr IValueT Rn = RegARM32::Encoded_Reg_pc;
+  IValueT Rm;
+  if (decodeOperand(OpSrc0, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  switch (typeWidthInBytes(OpSrc0->getType())) {
+  default:
+    return setNeedsTextFixup();
+  case 1: {
+    // UXTB - ARM section A8.8.274, encoding A1:
+    //   uxtb<c> <Rd>, <Rm>{, <rotate>}
+    //
+    // cccc011011101111ddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
+    // rr defined (RotationValue) rotate.
+    constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21;
+    emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
+    return;
+  }
+  case 2: {
+    // UXTH - ARM section A8.8.276, encoding A1:
+    //   uxth<c> <Rd>< <Rm>{, <rotate>}
+    //
+    // cccc01101111nnnnddddrr000111mmmm where cccc=Cond, dddd=Rd, mmmm=Rm, and
+    // rr defined (RotationValue) rotate.
+    constexpr IValueT Opcode = B26 | B25 | B23 | B22 | B21 | B20;
+    emitUxt(Cond, Opcode, Rd, Rn, Rm, Rotation);
+    return;
+  }
+  }
+}
+
 } // end of namespace ARM32
 } // end of namespace Ice