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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <assert.h> | 5 #include <assert.h> |
6 #include <stdarg.h> | 6 #include <stdarg.h> |
7 #include <stdio.h> | 7 #include <stdio.h> |
8 #include <string.h> | 8 #include <string.h> |
9 | 9 |
10 #if V8_TARGET_ARCH_ARM64 | 10 #if V8_TARGET_ARCH_ARM64 |
11 | 11 |
12 #include "src/arm64/decoder-arm64-inl.h" | 12 #include "src/arm64/decoder-arm64-inl.h" |
13 #include "src/arm64/disasm-arm64.h" | 13 #include "src/arm64/disasm-arm64.h" |
14 #include "src/base/platform/platform.h" | 14 #include "src/base/platform/platform.h" |
15 #include "src/disasm.h" | 15 #include "src/disasm.h" |
16 #include "src/macro-assembler.h" | 16 #include "src/macro-assembler.h" |
17 | 17 |
18 namespace v8 { | 18 namespace v8 { |
19 namespace internal { | 19 namespace internal { |
20 | 20 |
21 | 21 |
22 Disassembler::Disassembler() { | 22 DisassemblingDecoder::DisassemblingDecoder() { |
23 buffer_size_ = 256; | 23 buffer_size_ = 256; |
24 buffer_ = reinterpret_cast<char*>(malloc(buffer_size_)); | 24 buffer_ = reinterpret_cast<char*>(malloc(buffer_size_)); |
25 buffer_pos_ = 0; | 25 buffer_pos_ = 0; |
26 own_buffer_ = true; | 26 own_buffer_ = true; |
27 } | 27 } |
28 | 28 |
29 | 29 |
30 Disassembler::Disassembler(char* text_buffer, int buffer_size) { | 30 DisassemblingDecoder::DisassemblingDecoder(char* text_buffer, int buffer_size) { |
31 buffer_size_ = buffer_size; | 31 buffer_size_ = buffer_size; |
32 buffer_ = text_buffer; | 32 buffer_ = text_buffer; |
33 buffer_pos_ = 0; | 33 buffer_pos_ = 0; |
34 own_buffer_ = false; | 34 own_buffer_ = false; |
35 } | 35 } |
36 | 36 |
37 | 37 |
38 Disassembler::~Disassembler() { | 38 DisassemblingDecoder::~DisassemblingDecoder() { |
39 if (own_buffer_) { | 39 if (own_buffer_) { |
40 free(buffer_); | 40 free(buffer_); |
41 } | 41 } |
42 } | 42 } |
43 | 43 |
44 | 44 |
45 char* Disassembler::GetOutput() { | 45 char* DisassemblingDecoder::GetOutput() { return buffer_; } |
46 return buffer_; | |
47 } | |
48 | 46 |
49 | 47 |
50 void Disassembler::VisitAddSubImmediate(Instruction* instr) { | 48 void DisassemblingDecoder::VisitAddSubImmediate(Instruction* instr) { |
51 bool rd_is_zr = RdIsZROrSP(instr); | 49 bool rd_is_zr = RdIsZROrSP(instr); |
52 bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) && | 50 bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) && |
53 (instr->ImmAddSub() == 0) ? true : false; | 51 (instr->ImmAddSub() == 0) ? true : false; |
54 const char *mnemonic = ""; | 52 const char *mnemonic = ""; |
55 const char *form = "'Rds, 'Rns, 'IAddSub"; | 53 const char *form = "'Rds, 'Rns, 'IAddSub"; |
56 const char *form_cmp = "'Rns, 'IAddSub"; | 54 const char *form_cmp = "'Rns, 'IAddSub"; |
57 const char *form_mov = "'Rds, 'Rns"; | 55 const char *form_mov = "'Rds, 'Rns"; |
58 | 56 |
59 switch (instr->Mask(AddSubImmediateMask)) { | 57 switch (instr->Mask(AddSubImmediateMask)) { |
60 case ADD_w_imm: | 58 case ADD_w_imm: |
(...skipping 24 matching lines...) Expand all Loading... |
85 form = form_cmp; | 83 form = form_cmp; |
86 } | 84 } |
87 break; | 85 break; |
88 } | 86 } |
89 default: UNREACHABLE(); | 87 default: UNREACHABLE(); |
90 } | 88 } |
91 Format(instr, mnemonic, form); | 89 Format(instr, mnemonic, form); |
92 } | 90 } |
93 | 91 |
94 | 92 |
95 void Disassembler::VisitAddSubShifted(Instruction* instr) { | 93 void DisassemblingDecoder::VisitAddSubShifted(Instruction* instr) { |
96 bool rd_is_zr = RdIsZROrSP(instr); | 94 bool rd_is_zr = RdIsZROrSP(instr); |
97 bool rn_is_zr = RnIsZROrSP(instr); | 95 bool rn_is_zr = RnIsZROrSP(instr); |
98 const char *mnemonic = ""; | 96 const char *mnemonic = ""; |
99 const char *form = "'Rd, 'Rn, 'Rm'HDP"; | 97 const char *form = "'Rd, 'Rn, 'Rm'HDP"; |
100 const char *form_cmp = "'Rn, 'Rm'HDP"; | 98 const char *form_cmp = "'Rn, 'Rm'HDP"; |
101 const char *form_neg = "'Rd, 'Rm'HDP"; | 99 const char *form_neg = "'Rd, 'Rm'HDP"; |
102 | 100 |
103 switch (instr->Mask(AddSubShiftedMask)) { | 101 switch (instr->Mask(AddSubShiftedMask)) { |
104 case ADD_w_shift: | 102 case ADD_w_shift: |
105 case ADD_x_shift: mnemonic = "add"; break; | 103 case ADD_x_shift: mnemonic = "add"; break; |
(...skipping 26 matching lines...) Expand all Loading... |
132 form = form_neg; | 130 form = form_neg; |
133 } | 131 } |
134 break; | 132 break; |
135 } | 133 } |
136 default: UNREACHABLE(); | 134 default: UNREACHABLE(); |
137 } | 135 } |
138 Format(instr, mnemonic, form); | 136 Format(instr, mnemonic, form); |
139 } | 137 } |
140 | 138 |
141 | 139 |
142 void Disassembler::VisitAddSubExtended(Instruction* instr) { | 140 void DisassemblingDecoder::VisitAddSubExtended(Instruction* instr) { |
143 bool rd_is_zr = RdIsZROrSP(instr); | 141 bool rd_is_zr = RdIsZROrSP(instr); |
144 const char *mnemonic = ""; | 142 const char *mnemonic = ""; |
145 Extend mode = static_cast<Extend>(instr->ExtendMode()); | 143 Extend mode = static_cast<Extend>(instr->ExtendMode()); |
146 const char *form = ((mode == UXTX) || (mode == SXTX)) ? | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ? |
147 "'Rds, 'Rns, 'Xm'Ext" : "'Rds, 'Rns, 'Wm'Ext"; | 145 "'Rds, 'Rns, 'Xm'Ext" : "'Rds, 'Rns, 'Wm'Ext"; |
148 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? | 146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? |
149 "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; | 147 "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; |
150 | 148 |
151 switch (instr->Mask(AddSubExtendedMask)) { | 149 switch (instr->Mask(AddSubExtendedMask)) { |
152 case ADD_w_ext: | 150 case ADD_w_ext: |
(...skipping 17 matching lines...) Expand all Loading... |
170 form = form_cmp; | 168 form = form_cmp; |
171 } | 169 } |
172 break; | 170 break; |
173 } | 171 } |
174 default: UNREACHABLE(); | 172 default: UNREACHABLE(); |
175 } | 173 } |
176 Format(instr, mnemonic, form); | 174 Format(instr, mnemonic, form); |
177 } | 175 } |
178 | 176 |
179 | 177 |
180 void Disassembler::VisitAddSubWithCarry(Instruction* instr) { | 178 void DisassemblingDecoder::VisitAddSubWithCarry(Instruction* instr) { |
181 bool rn_is_zr = RnIsZROrSP(instr); | 179 bool rn_is_zr = RnIsZROrSP(instr); |
182 const char *mnemonic = ""; | 180 const char *mnemonic = ""; |
183 const char *form = "'Rd, 'Rn, 'Rm"; | 181 const char *form = "'Rd, 'Rn, 'Rm"; |
184 const char *form_neg = "'Rd, 'Rm"; | 182 const char *form_neg = "'Rd, 'Rm"; |
185 | 183 |
186 switch (instr->Mask(AddSubWithCarryMask)) { | 184 switch (instr->Mask(AddSubWithCarryMask)) { |
187 case ADC_w: | 185 case ADC_w: |
188 case ADC_x: mnemonic = "adc"; break; | 186 case ADC_x: mnemonic = "adc"; break; |
189 case ADCS_w: | 187 case ADCS_w: |
190 case ADCS_x: mnemonic = "adcs"; break; | 188 case ADCS_x: mnemonic = "adcs"; break; |
(...skipping 14 matching lines...) Expand all Loading... |
205 form = form_neg; | 203 form = form_neg; |
206 } | 204 } |
207 break; | 205 break; |
208 } | 206 } |
209 default: UNREACHABLE(); | 207 default: UNREACHABLE(); |
210 } | 208 } |
211 Format(instr, mnemonic, form); | 209 Format(instr, mnemonic, form); |
212 } | 210 } |
213 | 211 |
214 | 212 |
215 void Disassembler::VisitLogicalImmediate(Instruction* instr) { | 213 void DisassemblingDecoder::VisitLogicalImmediate(Instruction* instr) { |
216 bool rd_is_zr = RdIsZROrSP(instr); | 214 bool rd_is_zr = RdIsZROrSP(instr); |
217 bool rn_is_zr = RnIsZROrSP(instr); | 215 bool rn_is_zr = RnIsZROrSP(instr); |
218 const char *mnemonic = ""; | 216 const char *mnemonic = ""; |
219 const char *form = "'Rds, 'Rn, 'ITri"; | 217 const char *form = "'Rds, 'Rn, 'ITri"; |
220 | 218 |
221 if (instr->ImmLogical() == 0) { | 219 if (instr->ImmLogical() == 0) { |
222 // The immediate encoded in the instruction is not in the expected format. | 220 // The immediate encoded in the instruction is not in the expected format. |
223 Format(instr, "unallocated", "(LogicalImmediate)"); | 221 Format(instr, "unallocated", "(LogicalImmediate)"); |
224 return; | 222 return; |
225 } | 223 } |
(...skipping 22 matching lines...) Expand all Loading... |
248 form = "'Rn, 'ITri"; | 246 form = "'Rn, 'ITri"; |
249 } | 247 } |
250 break; | 248 break; |
251 } | 249 } |
252 default: UNREACHABLE(); | 250 default: UNREACHABLE(); |
253 } | 251 } |
254 Format(instr, mnemonic, form); | 252 Format(instr, mnemonic, form); |
255 } | 253 } |
256 | 254 |
257 | 255 |
258 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) { | 256 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { |
259 DCHECK((reg_size == kXRegSizeInBits) || | 257 DCHECK((reg_size == kXRegSizeInBits) || |
260 ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff))); | 258 ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff))); |
261 | 259 |
262 // Test for movz: 16-bits set at positions 0, 16, 32 or 48. | 260 // Test for movz: 16-bits set at positions 0, 16, 32 or 48. |
263 if (((value & 0xffffffffffff0000UL) == 0UL) || | 261 if (((value & 0xffffffffffff0000UL) == 0UL) || |
264 ((value & 0xffffffff0000ffffUL) == 0UL) || | 262 ((value & 0xffffffff0000ffffUL) == 0UL) || |
265 ((value & 0xffff0000ffffffffUL) == 0UL) || | 263 ((value & 0xffff0000ffffffffUL) == 0UL) || |
266 ((value & 0x0000ffffffffffffUL) == 0UL)) { | 264 ((value & 0x0000ffffffffffffUL) == 0UL)) { |
267 return true; | 265 return true; |
268 } | 266 } |
269 | 267 |
270 // Test for movn: NOT(16-bits set at positions 0, 16, 32 or 48). | 268 // Test for movn: NOT(16-bits set at positions 0, 16, 32 or 48). |
271 if ((reg_size == kXRegSizeInBits) && | 269 if ((reg_size == kXRegSizeInBits) && |
272 (((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) || | 270 (((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) || |
273 ((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) || | 271 ((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) || |
274 ((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) || | 272 ((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) || |
275 ((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) { | 273 ((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) { |
276 return true; | 274 return true; |
277 } | 275 } |
278 if ((reg_size == kWRegSizeInBits) && | 276 if ((reg_size == kWRegSizeInBits) && |
279 (((value & 0xffff0000) == 0xffff0000) || | 277 (((value & 0xffff0000) == 0xffff0000) || |
280 ((value & 0x0000ffff) == 0x0000ffff))) { | 278 ((value & 0x0000ffff) == 0x0000ffff))) { |
281 return true; | 279 return true; |
282 } | 280 } |
283 return false; | 281 return false; |
284 } | 282 } |
285 | 283 |
286 | 284 |
287 void Disassembler::VisitLogicalShifted(Instruction* instr) { | 285 void DisassemblingDecoder::VisitLogicalShifted(Instruction* instr) { |
288 bool rd_is_zr = RdIsZROrSP(instr); | 286 bool rd_is_zr = RdIsZROrSP(instr); |
289 bool rn_is_zr = RnIsZROrSP(instr); | 287 bool rn_is_zr = RnIsZROrSP(instr); |
290 const char *mnemonic = ""; | 288 const char *mnemonic = ""; |
291 const char *form = "'Rd, 'Rn, 'Rm'HLo"; | 289 const char *form = "'Rd, 'Rn, 'Rm'HLo"; |
292 | 290 |
293 switch (instr->Mask(LogicalShiftedMask)) { | 291 switch (instr->Mask(LogicalShiftedMask)) { |
294 case AND_w: | 292 case AND_w: |
295 case AND_x: mnemonic = "and"; break; | 293 case AND_x: mnemonic = "and"; break; |
296 case BIC_w: | 294 case BIC_w: |
297 case BIC_x: mnemonic = "bic"; break; | 295 case BIC_x: mnemonic = "bic"; break; |
(...skipping 30 matching lines...) Expand all Loading... |
328 } | 326 } |
329 break; | 327 break; |
330 } | 328 } |
331 default: UNREACHABLE(); | 329 default: UNREACHABLE(); |
332 } | 330 } |
333 | 331 |
334 Format(instr, mnemonic, form); | 332 Format(instr, mnemonic, form); |
335 } | 333 } |
336 | 334 |
337 | 335 |
338 void Disassembler::VisitConditionalCompareRegister(Instruction* instr) { | 336 void DisassemblingDecoder::VisitConditionalCompareRegister(Instruction* instr) { |
339 const char *mnemonic = ""; | 337 const char *mnemonic = ""; |
340 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond"; | 338 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond"; |
341 | 339 |
342 switch (instr->Mask(ConditionalCompareRegisterMask)) { | 340 switch (instr->Mask(ConditionalCompareRegisterMask)) { |
343 case CCMN_w: | 341 case CCMN_w: |
344 case CCMN_x: mnemonic = "ccmn"; break; | 342 case CCMN_x: mnemonic = "ccmn"; break; |
345 case CCMP_w: | 343 case CCMP_w: |
346 case CCMP_x: mnemonic = "ccmp"; break; | 344 case CCMP_x: mnemonic = "ccmp"; break; |
347 default: UNREACHABLE(); | 345 default: UNREACHABLE(); |
348 } | 346 } |
349 Format(instr, mnemonic, form); | 347 Format(instr, mnemonic, form); |
350 } | 348 } |
351 | 349 |
352 | 350 |
353 void Disassembler::VisitConditionalCompareImmediate(Instruction* instr) { | 351 void DisassemblingDecoder::VisitConditionalCompareImmediate( |
| 352 Instruction* instr) { |
354 const char *mnemonic = ""; | 353 const char *mnemonic = ""; |
355 const char *form = "'Rn, 'IP, 'INzcv, 'Cond"; | 354 const char *form = "'Rn, 'IP, 'INzcv, 'Cond"; |
356 | 355 |
357 switch (instr->Mask(ConditionalCompareImmediateMask)) { | 356 switch (instr->Mask(ConditionalCompareImmediateMask)) { |
358 case CCMN_w_imm: | 357 case CCMN_w_imm: |
359 case CCMN_x_imm: mnemonic = "ccmn"; break; | 358 case CCMN_x_imm: mnemonic = "ccmn"; break; |
360 case CCMP_w_imm: | 359 case CCMP_w_imm: |
361 case CCMP_x_imm: mnemonic = "ccmp"; break; | 360 case CCMP_x_imm: mnemonic = "ccmp"; break; |
362 default: UNREACHABLE(); | 361 default: UNREACHABLE(); |
363 } | 362 } |
364 Format(instr, mnemonic, form); | 363 Format(instr, mnemonic, form); |
365 } | 364 } |
366 | 365 |
367 | 366 |
368 void Disassembler::VisitConditionalSelect(Instruction* instr) { | 367 void DisassemblingDecoder::VisitConditionalSelect(Instruction* instr) { |
369 bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr)); | 368 bool rnm_is_zr = (RnIsZROrSP(instr) && RmIsZROrSP(instr)); |
370 bool rn_is_rm = (instr->Rn() == instr->Rm()); | 369 bool rn_is_rm = (instr->Rn() == instr->Rm()); |
371 const char *mnemonic = ""; | 370 const char *mnemonic = ""; |
372 const char *form = "'Rd, 'Rn, 'Rm, 'Cond"; | 371 const char *form = "'Rd, 'Rn, 'Rm, 'Cond"; |
373 const char *form_test = "'Rd, 'CInv"; | 372 const char *form_test = "'Rd, 'CInv"; |
374 const char *form_update = "'Rd, 'Rn, 'CInv"; | 373 const char *form_update = "'Rd, 'Rn, 'CInv"; |
375 | 374 |
376 Condition cond = static_cast<Condition>(instr->Condition()); | 375 Condition cond = static_cast<Condition>(instr->Condition()); |
377 bool invertible_cond = (cond != al) && (cond != nv); | 376 bool invertible_cond = (cond != al) && (cond != nv); |
378 | 377 |
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
411 form = form_update; | 410 form = form_update; |
412 } | 411 } |
413 break; | 412 break; |
414 } | 413 } |
415 default: UNREACHABLE(); | 414 default: UNREACHABLE(); |
416 } | 415 } |
417 Format(instr, mnemonic, form); | 416 Format(instr, mnemonic, form); |
418 } | 417 } |
419 | 418 |
420 | 419 |
421 void Disassembler::VisitBitfield(Instruction* instr) { | 420 void DisassemblingDecoder::VisitBitfield(Instruction* instr) { |
422 unsigned s = instr->ImmS(); | 421 unsigned s = instr->ImmS(); |
423 unsigned r = instr->ImmR(); | 422 unsigned r = instr->ImmR(); |
424 unsigned rd_size_minus_1 = | 423 unsigned rd_size_minus_1 = |
425 ((instr->SixtyFourBits() == 1) ? kXRegSizeInBits : kWRegSizeInBits) - 1; | 424 ((instr->SixtyFourBits() == 1) ? kXRegSizeInBits : kWRegSizeInBits) - 1; |
426 const char *mnemonic = ""; | 425 const char *mnemonic = ""; |
427 const char *form = ""; | 426 const char *form = ""; |
428 const char *form_shift_right = "'Rd, 'Rn, 'IBr"; | 427 const char *form_shift_right = "'Rd, 'Rn, 'IBr"; |
429 const char *form_extend = "'Rd, 'Wn"; | 428 const char *form_extend = "'Rd, 'Wn"; |
430 const char *form_bfiz = "'Rd, 'Rn, 'IBZ-r, 'IBs+1"; | 429 const char *form_bfiz = "'Rd, 'Rn, 'IBZ-r, 'IBs+1"; |
431 const char *form_bfx = "'Rd, 'Rn, 'IBr, 'IBs-r+1"; | 430 const char *form_bfx = "'Rd, 'Rn, 'IBr, 'IBs-r+1"; |
(...skipping 57 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
489 if (s < r) { | 488 if (s < r) { |
490 mnemonic = "bfi"; | 489 mnemonic = "bfi"; |
491 form = form_bfiz; | 490 form = form_bfiz; |
492 } | 491 } |
493 } | 492 } |
494 } | 493 } |
495 Format(instr, mnemonic, form); | 494 Format(instr, mnemonic, form); |
496 } | 495 } |
497 | 496 |
498 | 497 |
499 void Disassembler::VisitExtract(Instruction* instr) { | 498 void DisassemblingDecoder::VisitExtract(Instruction* instr) { |
500 const char *mnemonic = ""; | 499 const char *mnemonic = ""; |
501 const char *form = "'Rd, 'Rn, 'Rm, 'IExtract"; | 500 const char *form = "'Rd, 'Rn, 'Rm, 'IExtract"; |
502 | 501 |
503 switch (instr->Mask(ExtractMask)) { | 502 switch (instr->Mask(ExtractMask)) { |
504 case EXTR_w: | 503 case EXTR_w: |
505 case EXTR_x: { | 504 case EXTR_x: { |
506 if (instr->Rn() == instr->Rm()) { | 505 if (instr->Rn() == instr->Rm()) { |
507 mnemonic = "ror"; | 506 mnemonic = "ror"; |
508 form = "'Rd, 'Rn, 'IExtract"; | 507 form = "'Rd, 'Rn, 'IExtract"; |
509 } else { | 508 } else { |
510 mnemonic = "extr"; | 509 mnemonic = "extr"; |
511 } | 510 } |
512 break; | 511 break; |
513 } | 512 } |
514 default: UNREACHABLE(); | 513 default: UNREACHABLE(); |
515 } | 514 } |
516 Format(instr, mnemonic, form); | 515 Format(instr, mnemonic, form); |
517 } | 516 } |
518 | 517 |
519 | 518 |
520 void Disassembler::VisitPCRelAddressing(Instruction* instr) { | 519 void DisassemblingDecoder::VisitPCRelAddressing(Instruction* instr) { |
521 switch (instr->Mask(PCRelAddressingMask)) { | 520 switch (instr->Mask(PCRelAddressingMask)) { |
522 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; | 521 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; |
523 // ADRP is not implemented. | 522 // ADRP is not implemented. |
524 default: Format(instr, "unimplemented", "(PCRelAddressing)"); | 523 default: Format(instr, "unimplemented", "(PCRelAddressing)"); |
525 } | 524 } |
526 } | 525 } |
527 | 526 |
528 | 527 |
529 void Disassembler::VisitConditionalBranch(Instruction* instr) { | 528 void DisassemblingDecoder::VisitConditionalBranch(Instruction* instr) { |
530 switch (instr->Mask(ConditionalBranchMask)) { | 529 switch (instr->Mask(ConditionalBranchMask)) { |
531 case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break; | 530 case B_cond: Format(instr, "b.'CBrn", "'BImmCond"); break; |
532 default: UNREACHABLE(); | 531 default: UNREACHABLE(); |
533 } | 532 } |
534 } | 533 } |
535 | 534 |
536 | 535 |
537 void Disassembler::VisitUnconditionalBranchToRegister(Instruction* instr) { | 536 void DisassemblingDecoder::VisitUnconditionalBranchToRegister( |
| 537 Instruction* instr) { |
538 const char *mnemonic = "unimplemented"; | 538 const char *mnemonic = "unimplemented"; |
539 const char *form = "'Xn"; | 539 const char *form = "'Xn"; |
540 | 540 |
541 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { | 541 switch (instr->Mask(UnconditionalBranchToRegisterMask)) { |
542 case BR: mnemonic = "br"; break; | 542 case BR: mnemonic = "br"; break; |
543 case BLR: mnemonic = "blr"; break; | 543 case BLR: mnemonic = "blr"; break; |
544 case RET: { | 544 case RET: { |
545 mnemonic = "ret"; | 545 mnemonic = "ret"; |
546 if (instr->Rn() == kLinkRegCode) { | 546 if (instr->Rn() == kLinkRegCode) { |
547 form = NULL; | 547 form = NULL; |
548 } | 548 } |
549 break; | 549 break; |
550 } | 550 } |
551 default: form = "(UnconditionalBranchToRegister)"; | 551 default: form = "(UnconditionalBranchToRegister)"; |
552 } | 552 } |
553 Format(instr, mnemonic, form); | 553 Format(instr, mnemonic, form); |
554 } | 554 } |
555 | 555 |
556 | 556 |
557 void Disassembler::VisitUnconditionalBranch(Instruction* instr) { | 557 void DisassemblingDecoder::VisitUnconditionalBranch(Instruction* instr) { |
558 const char *mnemonic = ""; | 558 const char *mnemonic = ""; |
559 const char *form = "'BImmUncn"; | 559 const char *form = "'BImmUncn"; |
560 | 560 |
561 switch (instr->Mask(UnconditionalBranchMask)) { | 561 switch (instr->Mask(UnconditionalBranchMask)) { |
562 case B: mnemonic = "b"; break; | 562 case B: mnemonic = "b"; break; |
563 case BL: mnemonic = "bl"; break; | 563 case BL: mnemonic = "bl"; break; |
564 default: UNREACHABLE(); | 564 default: UNREACHABLE(); |
565 } | 565 } |
566 Format(instr, mnemonic, form); | 566 Format(instr, mnemonic, form); |
567 } | 567 } |
568 | 568 |
569 | 569 |
570 void Disassembler::VisitDataProcessing1Source(Instruction* instr) { | 570 void DisassemblingDecoder::VisitDataProcessing1Source(Instruction* instr) { |
571 const char *mnemonic = ""; | 571 const char *mnemonic = ""; |
572 const char *form = "'Rd, 'Rn"; | 572 const char *form = "'Rd, 'Rn"; |
573 | 573 |
574 switch (instr->Mask(DataProcessing1SourceMask)) { | 574 switch (instr->Mask(DataProcessing1SourceMask)) { |
575 #define FORMAT(A, B) \ | 575 #define FORMAT(A, B) \ |
576 case A##_w: \ | 576 case A##_w: \ |
577 case A##_x: mnemonic = B; break; | 577 case A##_x: mnemonic = B; break; |
578 FORMAT(RBIT, "rbit"); | 578 FORMAT(RBIT, "rbit"); |
579 FORMAT(REV16, "rev16"); | 579 FORMAT(REV16, "rev16"); |
580 FORMAT(REV, "rev"); | 580 FORMAT(REV, "rev"); |
581 FORMAT(CLZ, "clz"); | 581 FORMAT(CLZ, "clz"); |
582 FORMAT(CLS, "cls"); | 582 FORMAT(CLS, "cls"); |
583 #undef FORMAT | 583 #undef FORMAT |
584 case REV32_x: mnemonic = "rev32"; break; | 584 case REV32_x: mnemonic = "rev32"; break; |
585 default: UNREACHABLE(); | 585 default: UNREACHABLE(); |
586 } | 586 } |
587 Format(instr, mnemonic, form); | 587 Format(instr, mnemonic, form); |
588 } | 588 } |
589 | 589 |
590 | 590 |
591 void Disassembler::VisitDataProcessing2Source(Instruction* instr) { | 591 void DisassemblingDecoder::VisitDataProcessing2Source(Instruction* instr) { |
592 const char *mnemonic = "unimplemented"; | 592 const char *mnemonic = "unimplemented"; |
593 const char *form = "'Rd, 'Rn, 'Rm"; | 593 const char *form = "'Rd, 'Rn, 'Rm"; |
594 | 594 |
595 switch (instr->Mask(DataProcessing2SourceMask)) { | 595 switch (instr->Mask(DataProcessing2SourceMask)) { |
596 #define FORMAT(A, B) \ | 596 #define FORMAT(A, B) \ |
597 case A##_w: \ | 597 case A##_w: \ |
598 case A##_x: mnemonic = B; break; | 598 case A##_x: mnemonic = B; break; |
599 FORMAT(UDIV, "udiv"); | 599 FORMAT(UDIV, "udiv"); |
600 FORMAT(SDIV, "sdiv"); | 600 FORMAT(SDIV, "sdiv"); |
601 FORMAT(LSLV, "lsl"); | 601 FORMAT(LSLV, "lsl"); |
602 FORMAT(LSRV, "lsr"); | 602 FORMAT(LSRV, "lsr"); |
603 FORMAT(ASRV, "asr"); | 603 FORMAT(ASRV, "asr"); |
604 FORMAT(RORV, "ror"); | 604 FORMAT(RORV, "ror"); |
605 #undef FORMAT | 605 #undef FORMAT |
606 default: form = "(DataProcessing2Source)"; | 606 default: form = "(DataProcessing2Source)"; |
607 } | 607 } |
608 Format(instr, mnemonic, form); | 608 Format(instr, mnemonic, form); |
609 } | 609 } |
610 | 610 |
611 | 611 |
612 void Disassembler::VisitDataProcessing3Source(Instruction* instr) { | 612 void DisassemblingDecoder::VisitDataProcessing3Source(Instruction* instr) { |
613 bool ra_is_zr = RaIsZROrSP(instr); | 613 bool ra_is_zr = RaIsZROrSP(instr); |
614 const char *mnemonic = ""; | 614 const char *mnemonic = ""; |
615 const char *form = "'Xd, 'Wn, 'Wm, 'Xa"; | 615 const char *form = "'Xd, 'Wn, 'Wm, 'Xa"; |
616 const char *form_rrr = "'Rd, 'Rn, 'Rm"; | 616 const char *form_rrr = "'Rd, 'Rn, 'Rm"; |
617 const char *form_rrrr = "'Rd, 'Rn, 'Rm, 'Ra"; | 617 const char *form_rrrr = "'Rd, 'Rn, 'Rm, 'Ra"; |
618 const char *form_xww = "'Xd, 'Wn, 'Wm"; | 618 const char *form_xww = "'Xd, 'Wn, 'Wm"; |
619 const char *form_xxx = "'Xd, 'Xn, 'Xm"; | 619 const char *form_xxx = "'Xd, 'Xn, 'Xm"; |
620 | 620 |
621 switch (instr->Mask(DataProcessing3SourceMask)) { | 621 switch (instr->Mask(DataProcessing3SourceMask)) { |
622 case MADD_w: | 622 case MADD_w: |
(...skipping 57 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
680 mnemonic = "umulh"; | 680 mnemonic = "umulh"; |
681 form = form_xxx; | 681 form = form_xxx; |
682 break; | 682 break; |
683 } | 683 } |
684 default: UNREACHABLE(); | 684 default: UNREACHABLE(); |
685 } | 685 } |
686 Format(instr, mnemonic, form); | 686 Format(instr, mnemonic, form); |
687 } | 687 } |
688 | 688 |
689 | 689 |
690 void Disassembler::VisitCompareBranch(Instruction* instr) { | 690 void DisassemblingDecoder::VisitCompareBranch(Instruction* instr) { |
691 const char *mnemonic = ""; | 691 const char *mnemonic = ""; |
692 const char *form = "'Rt, 'BImmCmpa"; | 692 const char *form = "'Rt, 'BImmCmpa"; |
693 | 693 |
694 switch (instr->Mask(CompareBranchMask)) { | 694 switch (instr->Mask(CompareBranchMask)) { |
695 case CBZ_w: | 695 case CBZ_w: |
696 case CBZ_x: mnemonic = "cbz"; break; | 696 case CBZ_x: mnemonic = "cbz"; break; |
697 case CBNZ_w: | 697 case CBNZ_w: |
698 case CBNZ_x: mnemonic = "cbnz"; break; | 698 case CBNZ_x: mnemonic = "cbnz"; break; |
699 default: UNREACHABLE(); | 699 default: UNREACHABLE(); |
700 } | 700 } |
701 Format(instr, mnemonic, form); | 701 Format(instr, mnemonic, form); |
702 } | 702 } |
703 | 703 |
704 | 704 |
705 void Disassembler::VisitTestBranch(Instruction* instr) { | 705 void DisassemblingDecoder::VisitTestBranch(Instruction* instr) { |
706 const char *mnemonic = ""; | 706 const char *mnemonic = ""; |
707 // If the top bit of the immediate is clear, the tested register is | 707 // If the top bit of the immediate is clear, the tested register is |
708 // disassembled as Wt, otherwise Xt. As the top bit of the immediate is | 708 // disassembled as Wt, otherwise Xt. As the top bit of the immediate is |
709 // encoded in bit 31 of the instruction, we can reuse the Rt form, which | 709 // encoded in bit 31 of the instruction, we can reuse the Rt form, which |
710 // uses bit 31 (normally "sf") to choose the register size. | 710 // uses bit 31 (normally "sf") to choose the register size. |
711 const char *form = "'Rt, 'IS, 'BImmTest"; | 711 const char *form = "'Rt, 'IS, 'BImmTest"; |
712 | 712 |
713 switch (instr->Mask(TestBranchMask)) { | 713 switch (instr->Mask(TestBranchMask)) { |
714 case TBZ: mnemonic = "tbz"; break; | 714 case TBZ: mnemonic = "tbz"; break; |
715 case TBNZ: mnemonic = "tbnz"; break; | 715 case TBNZ: mnemonic = "tbnz"; break; |
716 default: UNREACHABLE(); | 716 default: UNREACHABLE(); |
717 } | 717 } |
718 Format(instr, mnemonic, form); | 718 Format(instr, mnemonic, form); |
719 } | 719 } |
720 | 720 |
721 | 721 |
722 void Disassembler::VisitMoveWideImmediate(Instruction* instr) { | 722 void DisassemblingDecoder::VisitMoveWideImmediate(Instruction* instr) { |
723 const char *mnemonic = ""; | 723 const char *mnemonic = ""; |
724 const char *form = "'Rd, 'IMoveImm"; | 724 const char *form = "'Rd, 'IMoveImm"; |
725 | 725 |
726 // Print the shift separately for movk, to make it clear which half word will | 726 // Print the shift separately for movk, to make it clear which half word will |
727 // be overwritten. Movn and movz print the computed immediate, which includes | 727 // be overwritten. Movn and movz print the computed immediate, which includes |
728 // shift calculation. | 728 // shift calculation. |
729 switch (instr->Mask(MoveWideImmediateMask)) { | 729 switch (instr->Mask(MoveWideImmediateMask)) { |
730 case MOVN_w: | 730 case MOVN_w: |
731 case MOVN_x: mnemonic = "movn"; break; | 731 case MOVN_x: mnemonic = "movn"; break; |
732 case MOVZ_w: | 732 case MOVZ_w: |
(...skipping 18 matching lines...) Expand all Loading... |
751 V(LDRSB_x, "ldrsb", "'Xt") \ | 751 V(LDRSB_x, "ldrsb", "'Xt") \ |
752 V(LDRSH_x, "ldrsh", "'Xt") \ | 752 V(LDRSH_x, "ldrsh", "'Xt") \ |
753 V(LDRSW_x, "ldrsw", "'Xt") \ | 753 V(LDRSW_x, "ldrsw", "'Xt") \ |
754 V(LDRSB_w, "ldrsb", "'Wt") \ | 754 V(LDRSB_w, "ldrsb", "'Wt") \ |
755 V(LDRSH_w, "ldrsh", "'Wt") \ | 755 V(LDRSH_w, "ldrsh", "'Wt") \ |
756 V(STR_s, "str", "'St") \ | 756 V(STR_s, "str", "'St") \ |
757 V(STR_d, "str", "'Dt") \ | 757 V(STR_d, "str", "'Dt") \ |
758 V(LDR_s, "ldr", "'St") \ | 758 V(LDR_s, "ldr", "'St") \ |
759 V(LDR_d, "ldr", "'Dt") | 759 V(LDR_d, "ldr", "'Dt") |
760 | 760 |
761 void Disassembler::VisitLoadStorePreIndex(Instruction* instr) { | 761 void DisassemblingDecoder::VisitLoadStorePreIndex(Instruction* instr) { |
762 const char *mnemonic = "unimplemented"; | 762 const char *mnemonic = "unimplemented"; |
763 const char *form = "(LoadStorePreIndex)"; | 763 const char *form = "(LoadStorePreIndex)"; |
764 | 764 |
765 switch (instr->Mask(LoadStorePreIndexMask)) { | 765 switch (instr->Mask(LoadStorePreIndexMask)) { |
766 #define LS_PREINDEX(A, B, C) \ | 766 #define LS_PREINDEX(A, B, C) \ |
767 case A##_pre: mnemonic = B; form = C ", ['Xns'ILS]!"; break; | 767 case A##_pre: mnemonic = B; form = C ", ['Xns'ILS]!"; break; |
768 LOAD_STORE_LIST(LS_PREINDEX) | 768 LOAD_STORE_LIST(LS_PREINDEX) |
769 #undef LS_PREINDEX | 769 #undef LS_PREINDEX |
770 } | 770 } |
771 Format(instr, mnemonic, form); | 771 Format(instr, mnemonic, form); |
772 } | 772 } |
773 | 773 |
774 | 774 |
775 void Disassembler::VisitLoadStorePostIndex(Instruction* instr) { | 775 void DisassemblingDecoder::VisitLoadStorePostIndex(Instruction* instr) { |
776 const char *mnemonic = "unimplemented"; | 776 const char *mnemonic = "unimplemented"; |
777 const char *form = "(LoadStorePostIndex)"; | 777 const char *form = "(LoadStorePostIndex)"; |
778 | 778 |
779 switch (instr->Mask(LoadStorePostIndexMask)) { | 779 switch (instr->Mask(LoadStorePostIndexMask)) { |
780 #define LS_POSTINDEX(A, B, C) \ | 780 #define LS_POSTINDEX(A, B, C) \ |
781 case A##_post: mnemonic = B; form = C ", ['Xns]'ILS"; break; | 781 case A##_post: mnemonic = B; form = C ", ['Xns]'ILS"; break; |
782 LOAD_STORE_LIST(LS_POSTINDEX) | 782 LOAD_STORE_LIST(LS_POSTINDEX) |
783 #undef LS_POSTINDEX | 783 #undef LS_POSTINDEX |
784 } | 784 } |
785 Format(instr, mnemonic, form); | 785 Format(instr, mnemonic, form); |
786 } | 786 } |
787 | 787 |
788 | 788 |
789 void Disassembler::VisitLoadStoreUnsignedOffset(Instruction* instr) { | 789 void DisassemblingDecoder::VisitLoadStoreUnsignedOffset(Instruction* instr) { |
790 const char *mnemonic = "unimplemented"; | 790 const char *mnemonic = "unimplemented"; |
791 const char *form = "(LoadStoreUnsignedOffset)"; | 791 const char *form = "(LoadStoreUnsignedOffset)"; |
792 | 792 |
793 switch (instr->Mask(LoadStoreUnsignedOffsetMask)) { | 793 switch (instr->Mask(LoadStoreUnsignedOffsetMask)) { |
794 #define LS_UNSIGNEDOFFSET(A, B, C) \ | 794 #define LS_UNSIGNEDOFFSET(A, B, C) \ |
795 case A##_unsigned: mnemonic = B; form = C ", ['Xns'ILU]"; break; | 795 case A##_unsigned: mnemonic = B; form = C ", ['Xns'ILU]"; break; |
796 LOAD_STORE_LIST(LS_UNSIGNEDOFFSET) | 796 LOAD_STORE_LIST(LS_UNSIGNEDOFFSET) |
797 #undef LS_UNSIGNEDOFFSET | 797 #undef LS_UNSIGNEDOFFSET |
798 case PRFM_unsigned: mnemonic = "prfm"; form = "'PrefOp, ['Xn'ILU]"; | 798 case PRFM_unsigned: mnemonic = "prfm"; form = "'PrefOp, ['Xn'ILU]"; |
799 } | 799 } |
800 Format(instr, mnemonic, form); | 800 Format(instr, mnemonic, form); |
801 } | 801 } |
802 | 802 |
803 | 803 |
804 void Disassembler::VisitLoadStoreRegisterOffset(Instruction* instr) { | 804 void DisassemblingDecoder::VisitLoadStoreRegisterOffset(Instruction* instr) { |
805 const char *mnemonic = "unimplemented"; | 805 const char *mnemonic = "unimplemented"; |
806 const char *form = "(LoadStoreRegisterOffset)"; | 806 const char *form = "(LoadStoreRegisterOffset)"; |
807 | 807 |
808 switch (instr->Mask(LoadStoreRegisterOffsetMask)) { | 808 switch (instr->Mask(LoadStoreRegisterOffsetMask)) { |
809 #define LS_REGISTEROFFSET(A, B, C) \ | 809 #define LS_REGISTEROFFSET(A, B, C) \ |
810 case A##_reg: mnemonic = B; form = C ", ['Xns, 'Offsetreg]"; break; | 810 case A##_reg: mnemonic = B; form = C ", ['Xns, 'Offsetreg]"; break; |
811 LOAD_STORE_LIST(LS_REGISTEROFFSET) | 811 LOAD_STORE_LIST(LS_REGISTEROFFSET) |
812 #undef LS_REGISTEROFFSET | 812 #undef LS_REGISTEROFFSET |
813 case PRFM_reg: mnemonic = "prfm"; form = "'PrefOp, ['Xns, 'Offsetreg]"; | 813 case PRFM_reg: mnemonic = "prfm"; form = "'PrefOp, ['Xns, 'Offsetreg]"; |
814 } | 814 } |
815 Format(instr, mnemonic, form); | 815 Format(instr, mnemonic, form); |
816 } | 816 } |
817 | 817 |
818 | 818 |
819 void Disassembler::VisitLoadStoreUnscaledOffset(Instruction* instr) { | 819 void DisassemblingDecoder::VisitLoadStoreUnscaledOffset(Instruction* instr) { |
820 const char *mnemonic = "unimplemented"; | 820 const char *mnemonic = "unimplemented"; |
821 const char *form = "'Wt, ['Xns'ILS]"; | 821 const char *form = "'Wt, ['Xns'ILS]"; |
822 const char *form_x = "'Xt, ['Xns'ILS]"; | 822 const char *form_x = "'Xt, ['Xns'ILS]"; |
823 const char *form_s = "'St, ['Xns'ILS]"; | 823 const char *form_s = "'St, ['Xns'ILS]"; |
824 const char *form_d = "'Dt, ['Xns'ILS]"; | 824 const char *form_d = "'Dt, ['Xns'ILS]"; |
825 | 825 |
826 switch (instr->Mask(LoadStoreUnscaledOffsetMask)) { | 826 switch (instr->Mask(LoadStoreUnscaledOffsetMask)) { |
827 case STURB_w: mnemonic = "sturb"; break; | 827 case STURB_w: mnemonic = "sturb"; break; |
828 case STURH_w: mnemonic = "sturh"; break; | 828 case STURH_w: mnemonic = "sturh"; break; |
829 case STUR_w: mnemonic = "stur"; break; | 829 case STUR_w: mnemonic = "stur"; break; |
(...skipping 10 matching lines...) Expand all Loading... |
840 case LDURSB_w: mnemonic = "ldursb"; break; | 840 case LDURSB_w: mnemonic = "ldursb"; break; |
841 case LDURSH_x: form = form_x; // Fall through. | 841 case LDURSH_x: form = form_x; // Fall through. |
842 case LDURSH_w: mnemonic = "ldursh"; break; | 842 case LDURSH_w: mnemonic = "ldursh"; break; |
843 case LDURSW_x: mnemonic = "ldursw"; form = form_x; break; | 843 case LDURSW_x: mnemonic = "ldursw"; form = form_x; break; |
844 default: form = "(LoadStoreUnscaledOffset)"; | 844 default: form = "(LoadStoreUnscaledOffset)"; |
845 } | 845 } |
846 Format(instr, mnemonic, form); | 846 Format(instr, mnemonic, form); |
847 } | 847 } |
848 | 848 |
849 | 849 |
850 void Disassembler::VisitLoadLiteral(Instruction* instr) { | 850 void DisassemblingDecoder::VisitLoadLiteral(Instruction* instr) { |
851 const char *mnemonic = "ldr"; | 851 const char *mnemonic = "ldr"; |
852 const char *form = "(LoadLiteral)"; | 852 const char *form = "(LoadLiteral)"; |
853 | 853 |
854 switch (instr->Mask(LoadLiteralMask)) { | 854 switch (instr->Mask(LoadLiteralMask)) { |
855 case LDR_w_lit: form = "'Wt, 'ILLiteral 'LValue"; break; | 855 case LDR_w_lit: form = "'Wt, 'ILLiteral 'LValue"; break; |
856 case LDR_x_lit: form = "'Xt, 'ILLiteral 'LValue"; break; | 856 case LDR_x_lit: form = "'Xt, 'ILLiteral 'LValue"; break; |
857 case LDR_s_lit: form = "'St, 'ILLiteral 'LValue"; break; | 857 case LDR_s_lit: form = "'St, 'ILLiteral 'LValue"; break; |
858 case LDR_d_lit: form = "'Dt, 'ILLiteral 'LValue"; break; | 858 case LDR_d_lit: form = "'Dt, 'ILLiteral 'LValue"; break; |
859 default: mnemonic = "unimplemented"; | 859 default: mnemonic = "unimplemented"; |
860 } | 860 } |
861 Format(instr, mnemonic, form); | 861 Format(instr, mnemonic, form); |
862 } | 862 } |
863 | 863 |
864 | 864 |
865 #define LOAD_STORE_PAIR_LIST(V) \ | 865 #define LOAD_STORE_PAIR_LIST(V) \ |
866 V(STP_w, "stp", "'Wt, 'Wt2", "4") \ | 866 V(STP_w, "stp", "'Wt, 'Wt2", "4") \ |
867 V(LDP_w, "ldp", "'Wt, 'Wt2", "4") \ | 867 V(LDP_w, "ldp", "'Wt, 'Wt2", "4") \ |
868 V(LDPSW_x, "ldpsw", "'Xt, 'Xt2", "4") \ | 868 V(LDPSW_x, "ldpsw", "'Xt, 'Xt2", "4") \ |
869 V(STP_x, "stp", "'Xt, 'Xt2", "8") \ | 869 V(STP_x, "stp", "'Xt, 'Xt2", "8") \ |
870 V(LDP_x, "ldp", "'Xt, 'Xt2", "8") \ | 870 V(LDP_x, "ldp", "'Xt, 'Xt2", "8") \ |
871 V(STP_s, "stp", "'St, 'St2", "4") \ | 871 V(STP_s, "stp", "'St, 'St2", "4") \ |
872 V(LDP_s, "ldp", "'St, 'St2", "4") \ | 872 V(LDP_s, "ldp", "'St, 'St2", "4") \ |
873 V(STP_d, "stp", "'Dt, 'Dt2", "8") \ | 873 V(STP_d, "stp", "'Dt, 'Dt2", "8") \ |
874 V(LDP_d, "ldp", "'Dt, 'Dt2", "8") | 874 V(LDP_d, "ldp", "'Dt, 'Dt2", "8") |
875 | 875 |
876 void Disassembler::VisitLoadStorePairPostIndex(Instruction* instr) { | 876 void DisassemblingDecoder::VisitLoadStorePairPostIndex(Instruction* instr) { |
877 const char *mnemonic = "unimplemented"; | 877 const char *mnemonic = "unimplemented"; |
878 const char *form = "(LoadStorePairPostIndex)"; | 878 const char *form = "(LoadStorePairPostIndex)"; |
879 | 879 |
880 switch (instr->Mask(LoadStorePairPostIndexMask)) { | 880 switch (instr->Mask(LoadStorePairPostIndexMask)) { |
881 #define LSP_POSTINDEX(A, B, C, D) \ | 881 #define LSP_POSTINDEX(A, B, C, D) \ |
882 case A##_post: mnemonic = B; form = C ", ['Xns]'ILP" D; break; | 882 case A##_post: mnemonic = B; form = C ", ['Xns]'ILP" D; break; |
883 LOAD_STORE_PAIR_LIST(LSP_POSTINDEX) | 883 LOAD_STORE_PAIR_LIST(LSP_POSTINDEX) |
884 #undef LSP_POSTINDEX | 884 #undef LSP_POSTINDEX |
885 } | 885 } |
886 Format(instr, mnemonic, form); | 886 Format(instr, mnemonic, form); |
887 } | 887 } |
888 | 888 |
889 | 889 |
890 void Disassembler::VisitLoadStorePairPreIndex(Instruction* instr) { | 890 void DisassemblingDecoder::VisitLoadStorePairPreIndex(Instruction* instr) { |
891 const char *mnemonic = "unimplemented"; | 891 const char *mnemonic = "unimplemented"; |
892 const char *form = "(LoadStorePairPreIndex)"; | 892 const char *form = "(LoadStorePairPreIndex)"; |
893 | 893 |
894 switch (instr->Mask(LoadStorePairPreIndexMask)) { | 894 switch (instr->Mask(LoadStorePairPreIndexMask)) { |
895 #define LSP_PREINDEX(A, B, C, D) \ | 895 #define LSP_PREINDEX(A, B, C, D) \ |
896 case A##_pre: mnemonic = B; form = C ", ['Xns'ILP" D "]!"; break; | 896 case A##_pre: mnemonic = B; form = C ", ['Xns'ILP" D "]!"; break; |
897 LOAD_STORE_PAIR_LIST(LSP_PREINDEX) | 897 LOAD_STORE_PAIR_LIST(LSP_PREINDEX) |
898 #undef LSP_PREINDEX | 898 #undef LSP_PREINDEX |
899 } | 899 } |
900 Format(instr, mnemonic, form); | 900 Format(instr, mnemonic, form); |
901 } | 901 } |
902 | 902 |
903 | 903 |
904 void Disassembler::VisitLoadStorePairOffset(Instruction* instr) { | 904 void DisassemblingDecoder::VisitLoadStorePairOffset(Instruction* instr) { |
905 const char *mnemonic = "unimplemented"; | 905 const char *mnemonic = "unimplemented"; |
906 const char *form = "(LoadStorePairOffset)"; | 906 const char *form = "(LoadStorePairOffset)"; |
907 | 907 |
908 switch (instr->Mask(LoadStorePairOffsetMask)) { | 908 switch (instr->Mask(LoadStorePairOffsetMask)) { |
909 #define LSP_OFFSET(A, B, C, D) \ | 909 #define LSP_OFFSET(A, B, C, D) \ |
910 case A##_off: mnemonic = B; form = C ", ['Xns'ILP" D "]"; break; | 910 case A##_off: mnemonic = B; form = C ", ['Xns'ILP" D "]"; break; |
911 LOAD_STORE_PAIR_LIST(LSP_OFFSET) | 911 LOAD_STORE_PAIR_LIST(LSP_OFFSET) |
912 #undef LSP_OFFSET | 912 #undef LSP_OFFSET |
913 } | 913 } |
914 Format(instr, mnemonic, form); | 914 Format(instr, mnemonic, form); |
915 } | 915 } |
916 | 916 |
917 | 917 |
918 void Disassembler::VisitFPCompare(Instruction* instr) { | 918 void DisassemblingDecoder::VisitFPCompare(Instruction* instr) { |
919 const char *mnemonic = "unimplemented"; | 919 const char *mnemonic = "unimplemented"; |
920 const char *form = "'Fn, 'Fm"; | 920 const char *form = "'Fn, 'Fm"; |
921 const char *form_zero = "'Fn, #0.0"; | 921 const char *form_zero = "'Fn, #0.0"; |
922 | 922 |
923 switch (instr->Mask(FPCompareMask)) { | 923 switch (instr->Mask(FPCompareMask)) { |
924 case FCMP_s_zero: | 924 case FCMP_s_zero: |
925 case FCMP_d_zero: form = form_zero; // Fall through. | 925 case FCMP_d_zero: form = form_zero; // Fall through. |
926 case FCMP_s: | 926 case FCMP_s: |
927 case FCMP_d: mnemonic = "fcmp"; break; | 927 case FCMP_d: mnemonic = "fcmp"; break; |
928 default: form = "(FPCompare)"; | 928 default: form = "(FPCompare)"; |
929 } | 929 } |
930 Format(instr, mnemonic, form); | 930 Format(instr, mnemonic, form); |
931 } | 931 } |
932 | 932 |
933 | 933 |
934 void Disassembler::VisitFPConditionalCompare(Instruction* instr) { | 934 void DisassemblingDecoder::VisitFPConditionalCompare(Instruction* instr) { |
935 const char *mnemonic = "unimplemented"; | 935 const char *mnemonic = "unimplemented"; |
936 const char *form = "'Fn, 'Fm, 'INzcv, 'Cond"; | 936 const char *form = "'Fn, 'Fm, 'INzcv, 'Cond"; |
937 | 937 |
938 switch (instr->Mask(FPConditionalCompareMask)) { | 938 switch (instr->Mask(FPConditionalCompareMask)) { |
939 case FCCMP_s: | 939 case FCCMP_s: |
940 case FCCMP_d: mnemonic = "fccmp"; break; | 940 case FCCMP_d: mnemonic = "fccmp"; break; |
941 case FCCMPE_s: | 941 case FCCMPE_s: |
942 case FCCMPE_d: mnemonic = "fccmpe"; break; | 942 case FCCMPE_d: mnemonic = "fccmpe"; break; |
943 default: form = "(FPConditionalCompare)"; | 943 default: form = "(FPConditionalCompare)"; |
944 } | 944 } |
945 Format(instr, mnemonic, form); | 945 Format(instr, mnemonic, form); |
946 } | 946 } |
947 | 947 |
948 | 948 |
949 void Disassembler::VisitFPConditionalSelect(Instruction* instr) { | 949 void DisassemblingDecoder::VisitFPConditionalSelect(Instruction* instr) { |
950 const char *mnemonic = ""; | 950 const char *mnemonic = ""; |
951 const char *form = "'Fd, 'Fn, 'Fm, 'Cond"; | 951 const char *form = "'Fd, 'Fn, 'Fm, 'Cond"; |
952 | 952 |
953 switch (instr->Mask(FPConditionalSelectMask)) { | 953 switch (instr->Mask(FPConditionalSelectMask)) { |
954 case FCSEL_s: | 954 case FCSEL_s: |
955 case FCSEL_d: mnemonic = "fcsel"; break; | 955 case FCSEL_d: mnemonic = "fcsel"; break; |
956 default: UNREACHABLE(); | 956 default: UNREACHABLE(); |
957 } | 957 } |
958 Format(instr, mnemonic, form); | 958 Format(instr, mnemonic, form); |
959 } | 959 } |
960 | 960 |
961 | 961 |
962 void Disassembler::VisitFPDataProcessing1Source(Instruction* instr) { | 962 void DisassemblingDecoder::VisitFPDataProcessing1Source(Instruction* instr) { |
963 const char *mnemonic = "unimplemented"; | 963 const char *mnemonic = "unimplemented"; |
964 const char *form = "'Fd, 'Fn"; | 964 const char *form = "'Fd, 'Fn"; |
965 | 965 |
966 switch (instr->Mask(FPDataProcessing1SourceMask)) { | 966 switch (instr->Mask(FPDataProcessing1SourceMask)) { |
967 #define FORMAT(A, B) \ | 967 #define FORMAT(A, B) \ |
968 case A##_s: \ | 968 case A##_s: \ |
969 case A##_d: mnemonic = B; break; | 969 case A##_d: mnemonic = B; break; |
970 FORMAT(FMOV, "fmov"); | 970 FORMAT(FMOV, "fmov"); |
971 FORMAT(FABS, "fabs"); | 971 FORMAT(FABS, "fabs"); |
972 FORMAT(FNEG, "fneg"); | 972 FORMAT(FNEG, "fneg"); |
973 FORMAT(FSQRT, "fsqrt"); | 973 FORMAT(FSQRT, "fsqrt"); |
974 FORMAT(FRINTN, "frintn"); | 974 FORMAT(FRINTN, "frintn"); |
975 FORMAT(FRINTP, "frintp"); | 975 FORMAT(FRINTP, "frintp"); |
976 FORMAT(FRINTM, "frintm"); | 976 FORMAT(FRINTM, "frintm"); |
977 FORMAT(FRINTZ, "frintz"); | 977 FORMAT(FRINTZ, "frintz"); |
978 FORMAT(FRINTA, "frinta"); | 978 FORMAT(FRINTA, "frinta"); |
979 FORMAT(FRINTX, "frintx"); | 979 FORMAT(FRINTX, "frintx"); |
980 FORMAT(FRINTI, "frinti"); | 980 FORMAT(FRINTI, "frinti"); |
981 #undef FORMAT | 981 #undef FORMAT |
982 case FCVT_ds: mnemonic = "fcvt"; form = "'Dd, 'Sn"; break; | 982 case FCVT_ds: mnemonic = "fcvt"; form = "'Dd, 'Sn"; break; |
983 case FCVT_sd: mnemonic = "fcvt"; form = "'Sd, 'Dn"; break; | 983 case FCVT_sd: mnemonic = "fcvt"; form = "'Sd, 'Dn"; break; |
984 default: form = "(FPDataProcessing1Source)"; | 984 default: form = "(FPDataProcessing1Source)"; |
985 } | 985 } |
986 Format(instr, mnemonic, form); | 986 Format(instr, mnemonic, form); |
987 } | 987 } |
988 | 988 |
989 | 989 |
990 void Disassembler::VisitFPDataProcessing2Source(Instruction* instr) { | 990 void DisassemblingDecoder::VisitFPDataProcessing2Source(Instruction* instr) { |
991 const char *mnemonic = ""; | 991 const char *mnemonic = ""; |
992 const char *form = "'Fd, 'Fn, 'Fm"; | 992 const char *form = "'Fd, 'Fn, 'Fm"; |
993 | 993 |
994 switch (instr->Mask(FPDataProcessing2SourceMask)) { | 994 switch (instr->Mask(FPDataProcessing2SourceMask)) { |
995 #define FORMAT(A, B) \ | 995 #define FORMAT(A, B) \ |
996 case A##_s: \ | 996 case A##_s: \ |
997 case A##_d: mnemonic = B; break; | 997 case A##_d: mnemonic = B; break; |
998 FORMAT(FMUL, "fmul"); | 998 FORMAT(FMUL, "fmul"); |
999 FORMAT(FDIV, "fdiv"); | 999 FORMAT(FDIV, "fdiv"); |
1000 FORMAT(FADD, "fadd"); | 1000 FORMAT(FADD, "fadd"); |
1001 FORMAT(FSUB, "fsub"); | 1001 FORMAT(FSUB, "fsub"); |
1002 FORMAT(FMAX, "fmax"); | 1002 FORMAT(FMAX, "fmax"); |
1003 FORMAT(FMIN, "fmin"); | 1003 FORMAT(FMIN, "fmin"); |
1004 FORMAT(FMAXNM, "fmaxnm"); | 1004 FORMAT(FMAXNM, "fmaxnm"); |
1005 FORMAT(FMINNM, "fminnm"); | 1005 FORMAT(FMINNM, "fminnm"); |
1006 FORMAT(FNMUL, "fnmul"); | 1006 FORMAT(FNMUL, "fnmul"); |
1007 #undef FORMAT | 1007 #undef FORMAT |
1008 default: UNREACHABLE(); | 1008 default: UNREACHABLE(); |
1009 } | 1009 } |
1010 Format(instr, mnemonic, form); | 1010 Format(instr, mnemonic, form); |
1011 } | 1011 } |
1012 | 1012 |
1013 | 1013 |
1014 void Disassembler::VisitFPDataProcessing3Source(Instruction* instr) { | 1014 void DisassemblingDecoder::VisitFPDataProcessing3Source(Instruction* instr) { |
1015 const char *mnemonic = ""; | 1015 const char *mnemonic = ""; |
1016 const char *form = "'Fd, 'Fn, 'Fm, 'Fa"; | 1016 const char *form = "'Fd, 'Fn, 'Fm, 'Fa"; |
1017 | 1017 |
1018 switch (instr->Mask(FPDataProcessing3SourceMask)) { | 1018 switch (instr->Mask(FPDataProcessing3SourceMask)) { |
1019 #define FORMAT(A, B) \ | 1019 #define FORMAT(A, B) \ |
1020 case A##_s: \ | 1020 case A##_s: \ |
1021 case A##_d: mnemonic = B; break; | 1021 case A##_d: mnemonic = B; break; |
1022 FORMAT(FMADD, "fmadd"); | 1022 FORMAT(FMADD, "fmadd"); |
1023 FORMAT(FMSUB, "fmsub"); | 1023 FORMAT(FMSUB, "fmsub"); |
1024 FORMAT(FNMADD, "fnmadd"); | 1024 FORMAT(FNMADD, "fnmadd"); |
1025 FORMAT(FNMSUB, "fnmsub"); | 1025 FORMAT(FNMSUB, "fnmsub"); |
1026 #undef FORMAT | 1026 #undef FORMAT |
1027 default: UNREACHABLE(); | 1027 default: UNREACHABLE(); |
1028 } | 1028 } |
1029 Format(instr, mnemonic, form); | 1029 Format(instr, mnemonic, form); |
1030 } | 1030 } |
1031 | 1031 |
1032 | 1032 |
1033 void Disassembler::VisitFPImmediate(Instruction* instr) { | 1033 void DisassemblingDecoder::VisitFPImmediate(Instruction* instr) { |
1034 const char *mnemonic = ""; | 1034 const char *mnemonic = ""; |
1035 const char *form = "(FPImmediate)"; | 1035 const char *form = "(FPImmediate)"; |
1036 | 1036 |
1037 switch (instr->Mask(FPImmediateMask)) { | 1037 switch (instr->Mask(FPImmediateMask)) { |
1038 case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break; | 1038 case FMOV_s_imm: mnemonic = "fmov"; form = "'Sd, 'IFPSingle"; break; |
1039 case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break; | 1039 case FMOV_d_imm: mnemonic = "fmov"; form = "'Dd, 'IFPDouble"; break; |
1040 default: UNREACHABLE(); | 1040 default: UNREACHABLE(); |
1041 } | 1041 } |
1042 Format(instr, mnemonic, form); | 1042 Format(instr, mnemonic, form); |
1043 } | 1043 } |
1044 | 1044 |
1045 | 1045 |
1046 void Disassembler::VisitFPIntegerConvert(Instruction* instr) { | 1046 void DisassemblingDecoder::VisitFPIntegerConvert(Instruction* instr) { |
1047 const char *mnemonic = "unimplemented"; | 1047 const char *mnemonic = "unimplemented"; |
1048 const char *form = "(FPIntegerConvert)"; | 1048 const char *form = "(FPIntegerConvert)"; |
1049 const char *form_rf = "'Rd, 'Fn"; | 1049 const char *form_rf = "'Rd, 'Fn"; |
1050 const char *form_fr = "'Fd, 'Rn"; | 1050 const char *form_fr = "'Fd, 'Rn"; |
1051 | 1051 |
1052 switch (instr->Mask(FPIntegerConvertMask)) { | 1052 switch (instr->Mask(FPIntegerConvertMask)) { |
1053 case FMOV_ws: | 1053 case FMOV_ws: |
1054 case FMOV_xd: mnemonic = "fmov"; form = form_rf; break; | 1054 case FMOV_xd: mnemonic = "fmov"; form = form_rf; break; |
1055 case FMOV_sw: | 1055 case FMOV_sw: |
1056 case FMOV_dx: mnemonic = "fmov"; form = form_fr; break; | 1056 case FMOV_dx: mnemonic = "fmov"; form = form_fr; break; |
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1092 case SCVTF_dx: mnemonic = "scvtf"; form = form_fr; break; | 1092 case SCVTF_dx: mnemonic = "scvtf"; form = form_fr; break; |
1093 case UCVTF_sw: | 1093 case UCVTF_sw: |
1094 case UCVTF_sx: | 1094 case UCVTF_sx: |
1095 case UCVTF_dw: | 1095 case UCVTF_dw: |
1096 case UCVTF_dx: mnemonic = "ucvtf"; form = form_fr; break; | 1096 case UCVTF_dx: mnemonic = "ucvtf"; form = form_fr; break; |
1097 } | 1097 } |
1098 Format(instr, mnemonic, form); | 1098 Format(instr, mnemonic, form); |
1099 } | 1099 } |
1100 | 1100 |
1101 | 1101 |
1102 void Disassembler::VisitFPFixedPointConvert(Instruction* instr) { | 1102 void DisassemblingDecoder::VisitFPFixedPointConvert(Instruction* instr) { |
1103 const char *mnemonic = ""; | 1103 const char *mnemonic = ""; |
1104 const char *form = "'Rd, 'Fn, 'IFPFBits"; | 1104 const char *form = "'Rd, 'Fn, 'IFPFBits"; |
1105 const char *form_fr = "'Fd, 'Rn, 'IFPFBits"; | 1105 const char *form_fr = "'Fd, 'Rn, 'IFPFBits"; |
1106 | 1106 |
1107 switch (instr->Mask(FPFixedPointConvertMask)) { | 1107 switch (instr->Mask(FPFixedPointConvertMask)) { |
1108 case FCVTZS_ws_fixed: | 1108 case FCVTZS_ws_fixed: |
1109 case FCVTZS_xs_fixed: | 1109 case FCVTZS_xs_fixed: |
1110 case FCVTZS_wd_fixed: | 1110 case FCVTZS_wd_fixed: |
1111 case FCVTZS_xd_fixed: mnemonic = "fcvtzs"; break; | 1111 case FCVTZS_xd_fixed: mnemonic = "fcvtzs"; break; |
1112 case FCVTZU_ws_fixed: | 1112 case FCVTZU_ws_fixed: |
1113 case FCVTZU_xs_fixed: | 1113 case FCVTZU_xs_fixed: |
1114 case FCVTZU_wd_fixed: | 1114 case FCVTZU_wd_fixed: |
1115 case FCVTZU_xd_fixed: mnemonic = "fcvtzu"; break; | 1115 case FCVTZU_xd_fixed: mnemonic = "fcvtzu"; break; |
1116 case SCVTF_sw_fixed: | 1116 case SCVTF_sw_fixed: |
1117 case SCVTF_sx_fixed: | 1117 case SCVTF_sx_fixed: |
1118 case SCVTF_dw_fixed: | 1118 case SCVTF_dw_fixed: |
1119 case SCVTF_dx_fixed: mnemonic = "scvtf"; form = form_fr; break; | 1119 case SCVTF_dx_fixed: mnemonic = "scvtf"; form = form_fr; break; |
1120 case UCVTF_sw_fixed: | 1120 case UCVTF_sw_fixed: |
1121 case UCVTF_sx_fixed: | 1121 case UCVTF_sx_fixed: |
1122 case UCVTF_dw_fixed: | 1122 case UCVTF_dw_fixed: |
1123 case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break; | 1123 case UCVTF_dx_fixed: mnemonic = "ucvtf"; form = form_fr; break; |
1124 } | 1124 } |
1125 Format(instr, mnemonic, form); | 1125 Format(instr, mnemonic, form); |
1126 } | 1126 } |
1127 | 1127 |
1128 | 1128 |
1129 void Disassembler::VisitSystem(Instruction* instr) { | 1129 void DisassemblingDecoder::VisitSystem(Instruction* instr) { |
1130 // Some system instructions hijack their Op and Cp fields to represent a | 1130 // Some system instructions hijack their Op and Cp fields to represent a |
1131 // range of immediates instead of indicating a different instruction. This | 1131 // range of immediates instead of indicating a different instruction. This |
1132 // makes the decoding tricky. | 1132 // makes the decoding tricky. |
1133 const char *mnemonic = "unimplemented"; | 1133 const char *mnemonic = "unimplemented"; |
1134 const char *form = "(System)"; | 1134 const char *form = "(System)"; |
1135 | 1135 |
1136 if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) { | 1136 if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) { |
1137 switch (instr->Mask(SystemSysRegMask)) { | 1137 switch (instr->Mask(SystemSysRegMask)) { |
1138 case MRS: { | 1138 case MRS: { |
1139 mnemonic = "mrs"; | 1139 mnemonic = "mrs"; |
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1180 form = NULL; | 1180 form = NULL; |
1181 break; | 1181 break; |
1182 } | 1182 } |
1183 } | 1183 } |
1184 } | 1184 } |
1185 | 1185 |
1186 Format(instr, mnemonic, form); | 1186 Format(instr, mnemonic, form); |
1187 } | 1187 } |
1188 | 1188 |
1189 | 1189 |
1190 void Disassembler::VisitException(Instruction* instr) { | 1190 void DisassemblingDecoder::VisitException(Instruction* instr) { |
1191 const char *mnemonic = "unimplemented"; | 1191 const char *mnemonic = "unimplemented"; |
1192 const char *form = "'IDebug"; | 1192 const char *form = "'IDebug"; |
1193 | 1193 |
1194 switch (instr->Mask(ExceptionMask)) { | 1194 switch (instr->Mask(ExceptionMask)) { |
1195 case HLT: mnemonic = "hlt"; break; | 1195 case HLT: mnemonic = "hlt"; break; |
1196 case BRK: mnemonic = "brk"; break; | 1196 case BRK: mnemonic = "brk"; break; |
1197 case SVC: mnemonic = "svc"; break; | 1197 case SVC: mnemonic = "svc"; break; |
1198 case HVC: mnemonic = "hvc"; break; | 1198 case HVC: mnemonic = "hvc"; break; |
1199 case SMC: mnemonic = "smc"; break; | 1199 case SMC: mnemonic = "smc"; break; |
1200 case DCPS1: mnemonic = "dcps1"; form = "{'IDebug}"; break; | 1200 case DCPS1: mnemonic = "dcps1"; form = "{'IDebug}"; break; |
1201 case DCPS2: mnemonic = "dcps2"; form = "{'IDebug}"; break; | 1201 case DCPS2: mnemonic = "dcps2"; form = "{'IDebug}"; break; |
1202 case DCPS3: mnemonic = "dcps3"; form = "{'IDebug}"; break; | 1202 case DCPS3: mnemonic = "dcps3"; form = "{'IDebug}"; break; |
1203 default: form = "(Exception)"; | 1203 default: form = "(Exception)"; |
1204 } | 1204 } |
1205 Format(instr, mnemonic, form); | 1205 Format(instr, mnemonic, form); |
1206 } | 1206 } |
1207 | 1207 |
1208 | 1208 |
1209 void Disassembler::VisitUnimplemented(Instruction* instr) { | 1209 void DisassemblingDecoder::VisitUnimplemented(Instruction* instr) { |
1210 Format(instr, "unimplemented", "(Unimplemented)"); | 1210 Format(instr, "unimplemented", "(Unimplemented)"); |
1211 } | 1211 } |
1212 | 1212 |
1213 | 1213 |
1214 void Disassembler::VisitUnallocated(Instruction* instr) { | 1214 void DisassemblingDecoder::VisitUnallocated(Instruction* instr) { |
1215 Format(instr, "unallocated", "(Unallocated)"); | 1215 Format(instr, "unallocated", "(Unallocated)"); |
1216 } | 1216 } |
1217 | 1217 |
1218 | 1218 |
1219 void Disassembler::ProcessOutput(Instruction* /*instr*/) { | 1219 void DisassemblingDecoder::ProcessOutput(Instruction* /*instr*/) { |
1220 // The base disasm does nothing more than disassembling into a buffer. | 1220 // The base disasm does nothing more than disassembling into a buffer. |
1221 } | 1221 } |
1222 | 1222 |
1223 | 1223 |
1224 void Disassembler::Format(Instruction* instr, const char* mnemonic, | 1224 void DisassemblingDecoder::Format(Instruction* instr, const char* mnemonic, |
1225 const char* format) { | 1225 const char* format) { |
1226 // TODO(mcapewel) don't think I can use the instr address here - there needs | 1226 // TODO(mcapewel) don't think I can use the instr address here - there needs |
1227 // to be a base address too | 1227 // to be a base address too |
1228 DCHECK(mnemonic != NULL); | 1228 DCHECK(mnemonic != NULL); |
1229 ResetOutput(); | 1229 ResetOutput(); |
1230 Substitute(instr, mnemonic); | 1230 Substitute(instr, mnemonic); |
1231 if (format != NULL) { | 1231 if (format != NULL) { |
1232 buffer_[buffer_pos_++] = ' '; | 1232 buffer_[buffer_pos_++] = ' '; |
1233 Substitute(instr, format); | 1233 Substitute(instr, format); |
1234 } | 1234 } |
1235 buffer_[buffer_pos_] = 0; | 1235 buffer_[buffer_pos_] = 0; |
1236 ProcessOutput(instr); | 1236 ProcessOutput(instr); |
1237 } | 1237 } |
1238 | 1238 |
1239 | 1239 |
1240 void Disassembler::Substitute(Instruction* instr, const char* string) { | 1240 void DisassemblingDecoder::Substitute(Instruction* instr, const char* string) { |
1241 char chr = *string++; | 1241 char chr = *string++; |
1242 while (chr != '\0') { | 1242 while (chr != '\0') { |
1243 if (chr == '\'') { | 1243 if (chr == '\'') { |
1244 string += SubstituteField(instr, string); | 1244 string += SubstituteField(instr, string); |
1245 } else { | 1245 } else { |
1246 buffer_[buffer_pos_++] = chr; | 1246 buffer_[buffer_pos_++] = chr; |
1247 } | 1247 } |
1248 chr = *string++; | 1248 chr = *string++; |
1249 } | 1249 } |
1250 } | 1250 } |
1251 | 1251 |
1252 | 1252 |
1253 int Disassembler::SubstituteField(Instruction* instr, const char* format) { | 1253 int DisassemblingDecoder::SubstituteField(Instruction* instr, |
| 1254 const char* format) { |
1254 switch (format[0]) { | 1255 switch (format[0]) { |
1255 case 'R': // Register. X or W, selected by sf bit. | 1256 case 'R': // Register. X or W, selected by sf bit. |
1256 case 'F': // FP Register. S or D, selected by type field. | 1257 case 'F': // FP Register. S or D, selected by type field. |
1257 case 'W': | 1258 case 'W': |
1258 case 'X': | 1259 case 'X': |
1259 case 'S': | 1260 case 'S': |
1260 case 'D': return SubstituteRegisterField(instr, format); | 1261 case 'D': return SubstituteRegisterField(instr, format); |
1261 case 'I': return SubstituteImmediateField(instr, format); | 1262 case 'I': return SubstituteImmediateField(instr, format); |
1262 case 'L': return SubstituteLiteralField(instr, format); | 1263 case 'L': return SubstituteLiteralField(instr, format); |
1263 case 'H': return SubstituteShiftField(instr, format); | 1264 case 'H': return SubstituteShiftField(instr, format); |
1264 case 'P': return SubstitutePrefetchField(instr, format); | 1265 case 'P': return SubstitutePrefetchField(instr, format); |
1265 case 'C': return SubstituteConditionField(instr, format); | 1266 case 'C': return SubstituteConditionField(instr, format); |
1266 case 'E': return SubstituteExtendField(instr, format); | 1267 case 'E': return SubstituteExtendField(instr, format); |
1267 case 'A': return SubstitutePCRelAddressField(instr, format); | 1268 case 'A': return SubstitutePCRelAddressField(instr, format); |
1268 case 'B': return SubstituteBranchTargetField(instr, format); | 1269 case 'B': return SubstituteBranchTargetField(instr, format); |
1269 case 'O': return SubstituteLSRegOffsetField(instr, format); | 1270 case 'O': return SubstituteLSRegOffsetField(instr, format); |
1270 case 'M': return SubstituteBarrierField(instr, format); | 1271 case 'M': return SubstituteBarrierField(instr, format); |
1271 default: { | 1272 default: { |
1272 UNREACHABLE(); | 1273 UNREACHABLE(); |
1273 return 1; | 1274 return 1; |
1274 } | 1275 } |
1275 } | 1276 } |
1276 } | 1277 } |
1277 | 1278 |
1278 | 1279 |
1279 int Disassembler::SubstituteRegisterField(Instruction* instr, | 1280 int DisassemblingDecoder::SubstituteRegisterField(Instruction* instr, |
1280 const char* format) { | 1281 const char* format) { |
1281 unsigned reg_num = 0; | 1282 unsigned reg_num = 0; |
1282 unsigned field_len = 2; | 1283 unsigned field_len = 2; |
1283 switch (format[1]) { | 1284 switch (format[1]) { |
1284 case 'd': reg_num = instr->Rd(); break; | 1285 case 'd': reg_num = instr->Rd(); break; |
1285 case 'n': reg_num = instr->Rn(); break; | 1286 case 'n': reg_num = instr->Rn(); break; |
1286 case 'm': reg_num = instr->Rm(); break; | 1287 case 'm': reg_num = instr->Rm(); break; |
1287 case 'a': reg_num = instr->Ra(); break; | 1288 case 'a': reg_num = instr->Ra(); break; |
1288 case 't': { | 1289 case 't': { |
1289 if (format[2] == '2') { | 1290 if (format[2] == '2') { |
1290 reg_num = instr->Rt2(); | 1291 reg_num = instr->Rt2(); |
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1334 AppendToOutput("%s", (reg_type == 'w') ? "wcsp" : "csp"); | 1335 AppendToOutput("%s", (reg_type == 'w') ? "wcsp" : "csp"); |
1335 } else { | 1336 } else { |
1336 // Disassemble w31/x31 as zero register wzr/xzr. | 1337 // Disassemble w31/x31 as zero register wzr/xzr. |
1337 AppendToOutput("%czr", reg_type); | 1338 AppendToOutput("%czr", reg_type); |
1338 } | 1339 } |
1339 | 1340 |
1340 return field_len; | 1341 return field_len; |
1341 } | 1342 } |
1342 | 1343 |
1343 | 1344 |
1344 int Disassembler::SubstituteImmediateField(Instruction* instr, | 1345 int DisassemblingDecoder::SubstituteImmediateField(Instruction* instr, |
1345 const char* format) { | 1346 const char* format) { |
1346 DCHECK(format[0] == 'I'); | 1347 DCHECK(format[0] == 'I'); |
1347 | 1348 |
1348 switch (format[1]) { | 1349 switch (format[1]) { |
1349 case 'M': { // IMoveImm or IMoveLSL. | 1350 case 'M': { // IMoveImm or IMoveLSL. |
1350 if (format[5] == 'I') { | 1351 if (format[5] == 'I') { |
1351 uint64_t imm = static_cast<uint64_t>(instr->ImmMoveWide()) | 1352 uint64_t imm = static_cast<uint64_t>(instr->ImmMoveWide()) |
1352 << (16 * instr->ShiftMoveWide()); | 1353 << (16 * instr->ShiftMoveWide()); |
1353 AppendToOutput("#0x%" PRIx64, imm); | 1354 AppendToOutput("#0x%" PRIx64, imm); |
1354 } else { | 1355 } else { |
1355 DCHECK(format[5] == 'L'); | 1356 DCHECK(format[5] == 'L'); |
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1445 return 6; | 1446 return 6; |
1446 } | 1447 } |
1447 default: { | 1448 default: { |
1448 UNREACHABLE(); | 1449 UNREACHABLE(); |
1449 return 0; | 1450 return 0; |
1450 } | 1451 } |
1451 } | 1452 } |
1452 } | 1453 } |
1453 | 1454 |
1454 | 1455 |
1455 int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr, | 1456 int DisassemblingDecoder::SubstituteBitfieldImmediateField(Instruction* instr, |
1456 const char* format) { | 1457 const char* format) { |
1457 DCHECK((format[0] == 'I') && (format[1] == 'B')); | 1458 DCHECK((format[0] == 'I') && (format[1] == 'B')); |
1458 unsigned r = instr->ImmR(); | 1459 unsigned r = instr->ImmR(); |
1459 unsigned s = instr->ImmS(); | 1460 unsigned s = instr->ImmS(); |
1460 | 1461 |
1461 switch (format[2]) { | 1462 switch (format[2]) { |
1462 case 'r': { // IBr. | 1463 case 'r': { // IBr. |
1463 AppendToOutput("#%d", r); | 1464 AppendToOutput("#%d", r); |
1464 return 3; | 1465 return 3; |
1465 } | 1466 } |
1466 case 's': { // IBs+1 or IBs-r+1. | 1467 case 's': { // IBs+1 or IBs-r+1. |
(...skipping 14 matching lines...) Expand all Loading... |
1481 return 5; | 1482 return 5; |
1482 } | 1483 } |
1483 default: { | 1484 default: { |
1484 UNREACHABLE(); | 1485 UNREACHABLE(); |
1485 return 0; | 1486 return 0; |
1486 } | 1487 } |
1487 } | 1488 } |
1488 } | 1489 } |
1489 | 1490 |
1490 | 1491 |
1491 int Disassembler::SubstituteLiteralField(Instruction* instr, | 1492 int DisassemblingDecoder::SubstituteLiteralField(Instruction* instr, |
1492 const char* format) { | 1493 const char* format) { |
1493 DCHECK(strncmp(format, "LValue", 6) == 0); | 1494 DCHECK(strncmp(format, "LValue", 6) == 0); |
1494 USE(format); | 1495 USE(format); |
1495 | 1496 |
1496 switch (instr->Mask(LoadLiteralMask)) { | 1497 switch (instr->Mask(LoadLiteralMask)) { |
1497 case LDR_w_lit: | 1498 case LDR_w_lit: |
1498 case LDR_x_lit: | 1499 case LDR_x_lit: |
1499 case LDR_s_lit: | 1500 case LDR_s_lit: |
1500 case LDR_d_lit: | 1501 case LDR_d_lit: |
1501 AppendToOutput("(addr 0x%016" PRIxPTR ")", instr->LiteralAddress()); | 1502 AppendToOutput("(addr 0x%016" PRIxPTR ")", instr->LiteralAddress()); |
1502 break; | 1503 break; |
1503 default: UNREACHABLE(); | 1504 default: UNREACHABLE(); |
1504 } | 1505 } |
1505 | 1506 |
1506 return 6; | 1507 return 6; |
1507 } | 1508 } |
1508 | 1509 |
1509 | 1510 |
1510 int Disassembler::SubstituteShiftField(Instruction* instr, const char* format) { | 1511 int DisassemblingDecoder::SubstituteShiftField(Instruction* instr, |
| 1512 const char* format) { |
1511 DCHECK(format[0] == 'H'); | 1513 DCHECK(format[0] == 'H'); |
1512 DCHECK(instr->ShiftDP() <= 0x3); | 1514 DCHECK(instr->ShiftDP() <= 0x3); |
1513 | 1515 |
1514 switch (format[1]) { | 1516 switch (format[1]) { |
1515 case 'D': { // HDP. | 1517 case 'D': { // HDP. |
1516 DCHECK(instr->ShiftDP() != ROR); | 1518 DCHECK(instr->ShiftDP() != ROR); |
1517 } // Fall through. | 1519 } // Fall through. |
1518 case 'L': { // HLo. | 1520 case 'L': { // HLo. |
1519 if (instr->ImmDPShift() != 0) { | 1521 if (instr->ImmDPShift() != 0) { |
1520 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; | 1522 const char* shift_type[] = {"lsl", "lsr", "asr", "ror"}; |
1521 AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()], | 1523 AppendToOutput(", %s #%" PRId32, shift_type[instr->ShiftDP()], |
1522 instr->ImmDPShift()); | 1524 instr->ImmDPShift()); |
1523 } | 1525 } |
1524 return 3; | 1526 return 3; |
1525 } | 1527 } |
1526 default: | 1528 default: |
1527 UNREACHABLE(); | 1529 UNREACHABLE(); |
1528 return 0; | 1530 return 0; |
1529 } | 1531 } |
1530 } | 1532 } |
1531 | 1533 |
1532 | 1534 |
1533 int Disassembler::SubstituteConditionField(Instruction* instr, | 1535 int DisassemblingDecoder::SubstituteConditionField(Instruction* instr, |
1534 const char* format) { | 1536 const char* format) { |
1535 DCHECK(format[0] == 'C'); | 1537 DCHECK(format[0] == 'C'); |
1536 const char* condition_code[] = { "eq", "ne", "hs", "lo", | 1538 const char* condition_code[] = { "eq", "ne", "hs", "lo", |
1537 "mi", "pl", "vs", "vc", | 1539 "mi", "pl", "vs", "vc", |
1538 "hi", "ls", "ge", "lt", | 1540 "hi", "ls", "ge", "lt", |
1539 "gt", "le", "al", "nv" }; | 1541 "gt", "le", "al", "nv" }; |
1540 int cond; | 1542 int cond; |
1541 switch (format[1]) { | 1543 switch (format[1]) { |
1542 case 'B': cond = instr->ConditionBranch(); break; | 1544 case 'B': cond = instr->ConditionBranch(); break; |
1543 case 'I': { | 1545 case 'I': { |
1544 cond = NegateCondition(static_cast<Condition>(instr->Condition())); | 1546 cond = NegateCondition(static_cast<Condition>(instr->Condition())); |
1545 break; | 1547 break; |
1546 } | 1548 } |
1547 default: cond = instr->Condition(); | 1549 default: cond = instr->Condition(); |
1548 } | 1550 } |
1549 AppendToOutput("%s", condition_code[cond]); | 1551 AppendToOutput("%s", condition_code[cond]); |
1550 return 4; | 1552 return 4; |
1551 } | 1553 } |
1552 | 1554 |
1553 | 1555 |
1554 int Disassembler::SubstitutePCRelAddressField(Instruction* instr, | 1556 int DisassemblingDecoder::SubstitutePCRelAddressField(Instruction* instr, |
1555 const char* format) { | 1557 const char* format) { |
1556 USE(format); | 1558 USE(format); |
1557 DCHECK(strncmp(format, "AddrPCRel", 9) == 0); | 1559 DCHECK(strncmp(format, "AddrPCRel", 9) == 0); |
1558 | 1560 |
1559 int offset = instr->ImmPCRel(); | 1561 int offset = instr->ImmPCRel(); |
1560 | 1562 |
1561 // Only ADR (AddrPCRelByte) is supported. | 1563 // Only ADR (AddrPCRelByte) is supported. |
1562 DCHECK(strcmp(format, "AddrPCRelByte") == 0); | 1564 DCHECK(strcmp(format, "AddrPCRelByte") == 0); |
1563 | 1565 |
1564 char sign = '+'; | 1566 char sign = '+'; |
1565 if (offset < 0) { | 1567 if (offset < 0) { |
1566 offset = -offset; | 1568 offset = -offset; |
1567 sign = '-'; | 1569 sign = '-'; |
1568 } | 1570 } |
1569 AppendToOutput("#%c0x%x (addr %p)", sign, offset, | 1571 AppendToOutput("#%c0x%x (addr %p)", sign, offset, |
1570 instr->InstructionAtOffset(offset, Instruction::NO_CHECK)); | 1572 instr->InstructionAtOffset(offset, Instruction::NO_CHECK)); |
1571 return 13; | 1573 return 13; |
1572 } | 1574 } |
1573 | 1575 |
1574 | 1576 |
1575 int Disassembler::SubstituteBranchTargetField(Instruction* instr, | 1577 int DisassemblingDecoder::SubstituteBranchTargetField(Instruction* instr, |
1576 const char* format) { | 1578 const char* format) { |
1577 DCHECK(strncmp(format, "BImm", 4) == 0); | 1579 DCHECK(strncmp(format, "BImm", 4) == 0); |
1578 | 1580 |
1579 int64_t offset = 0; | 1581 int64_t offset = 0; |
1580 switch (format[5]) { | 1582 switch (format[5]) { |
1581 // BImmUncn - unconditional branch immediate. | 1583 // BImmUncn - unconditional branch immediate. |
1582 case 'n': offset = instr->ImmUncondBranch(); break; | 1584 case 'n': offset = instr->ImmUncondBranch(); break; |
1583 // BImmCond - conditional branch immediate. | 1585 // BImmCond - conditional branch immediate. |
1584 case 'o': offset = instr->ImmCondBranch(); break; | 1586 case 'o': offset = instr->ImmCondBranch(); break; |
1585 // BImmCmpa - compare and branch immediate. | 1587 // BImmCmpa - compare and branch immediate. |
1586 case 'm': offset = instr->ImmCmpBranch(); break; | 1588 case 'm': offset = instr->ImmCmpBranch(); break; |
1587 // BImmTest - test and branch immediate. | 1589 // BImmTest - test and branch immediate. |
1588 case 'e': offset = instr->ImmTestBranch(); break; | 1590 case 'e': offset = instr->ImmTestBranch(); break; |
1589 default: UNREACHABLE(); | 1591 default: UNREACHABLE(); |
1590 } | 1592 } |
1591 offset <<= kInstructionSizeLog2; | 1593 offset <<= kInstructionSizeLog2; |
1592 char sign = '+'; | 1594 char sign = '+'; |
1593 if (offset < 0) { | 1595 if (offset < 0) { |
1594 sign = '-'; | 1596 sign = '-'; |
1595 } | 1597 } |
1596 AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, Abs(offset), | 1598 AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, Abs(offset), |
1597 instr->InstructionAtOffset(offset), Instruction::NO_CHECK); | 1599 instr->InstructionAtOffset(offset), Instruction::NO_CHECK); |
1598 return 8; | 1600 return 8; |
1599 } | 1601 } |
1600 | 1602 |
1601 | 1603 |
1602 int Disassembler::SubstituteExtendField(Instruction* instr, | 1604 int DisassemblingDecoder::SubstituteExtendField(Instruction* instr, |
1603 const char* format) { | 1605 const char* format) { |
1604 DCHECK(strncmp(format, "Ext", 3) == 0); | 1606 DCHECK(strncmp(format, "Ext", 3) == 0); |
1605 DCHECK(instr->ExtendMode() <= 7); | 1607 DCHECK(instr->ExtendMode() <= 7); |
1606 USE(format); | 1608 USE(format); |
1607 | 1609 |
1608 const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx", | 1610 const char* extend_mode[] = { "uxtb", "uxth", "uxtw", "uxtx", |
1609 "sxtb", "sxth", "sxtw", "sxtx" }; | 1611 "sxtb", "sxth", "sxtw", "sxtx" }; |
1610 | 1612 |
1611 // If rd or rn is SP, uxtw on 32-bit registers and uxtx on 64-bit | 1613 // If rd or rn is SP, uxtw on 32-bit registers and uxtx on 64-bit |
1612 // registers becomes lsl. | 1614 // registers becomes lsl. |
1613 if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) && | 1615 if (((instr->Rd() == kZeroRegCode) || (instr->Rn() == kZeroRegCode)) && |
1614 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || | 1616 (((instr->ExtendMode() == UXTW) && (instr->SixtyFourBits() == 0)) || |
1615 (instr->ExtendMode() == UXTX))) { | 1617 (instr->ExtendMode() == UXTX))) { |
1616 if (instr->ImmExtendShift() > 0) { | 1618 if (instr->ImmExtendShift() > 0) { |
1617 AppendToOutput(", lsl #%d", instr->ImmExtendShift()); | 1619 AppendToOutput(", lsl #%d", instr->ImmExtendShift()); |
1618 } | 1620 } |
1619 } else { | 1621 } else { |
1620 AppendToOutput(", %s", extend_mode[instr->ExtendMode()]); | 1622 AppendToOutput(", %s", extend_mode[instr->ExtendMode()]); |
1621 if (instr->ImmExtendShift() > 0) { | 1623 if (instr->ImmExtendShift() > 0) { |
1622 AppendToOutput(" #%d", instr->ImmExtendShift()); | 1624 AppendToOutput(" #%d", instr->ImmExtendShift()); |
1623 } | 1625 } |
1624 } | 1626 } |
1625 return 3; | 1627 return 3; |
1626 } | 1628 } |
1627 | 1629 |
1628 | 1630 |
1629 int Disassembler::SubstituteLSRegOffsetField(Instruction* instr, | 1631 int DisassemblingDecoder::SubstituteLSRegOffsetField(Instruction* instr, |
1630 const char* format) { | 1632 const char* format) { |
1631 DCHECK(strncmp(format, "Offsetreg", 9) == 0); | 1633 DCHECK(strncmp(format, "Offsetreg", 9) == 0); |
1632 const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl", | 1634 const char* extend_mode[] = { "undefined", "undefined", "uxtw", "lsl", |
1633 "undefined", "undefined", "sxtw", "sxtx" }; | 1635 "undefined", "undefined", "sxtw", "sxtx" }; |
1634 USE(format); | 1636 USE(format); |
1635 | 1637 |
1636 unsigned shift = instr->ImmShiftLS(); | 1638 unsigned shift = instr->ImmShiftLS(); |
1637 Extend ext = static_cast<Extend>(instr->ExtendMode()); | 1639 Extend ext = static_cast<Extend>(instr->ExtendMode()); |
1638 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; | 1640 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; |
1639 | 1641 |
1640 unsigned rm = instr->Rm(); | 1642 unsigned rm = instr->Rm(); |
1641 if (rm == kZeroRegCode) { | 1643 if (rm == kZeroRegCode) { |
1642 AppendToOutput("%czr", reg_type); | 1644 AppendToOutput("%czr", reg_type); |
1643 } else { | 1645 } else { |
1644 AppendToOutput("%c%d", reg_type, rm); | 1646 AppendToOutput("%c%d", reg_type, rm); |
1645 } | 1647 } |
1646 | 1648 |
1647 // Extend mode UXTX is an alias for shift mode LSL here. | 1649 // Extend mode UXTX is an alias for shift mode LSL here. |
1648 if (!((ext == UXTX) && (shift == 0))) { | 1650 if (!((ext == UXTX) && (shift == 0))) { |
1649 AppendToOutput(", %s", extend_mode[ext]); | 1651 AppendToOutput(", %s", extend_mode[ext]); |
1650 if (shift != 0) { | 1652 if (shift != 0) { |
1651 AppendToOutput(" #%d", instr->SizeLS()); | 1653 AppendToOutput(" #%d", instr->SizeLS()); |
1652 } | 1654 } |
1653 } | 1655 } |
1654 return 9; | 1656 return 9; |
1655 } | 1657 } |
1656 | 1658 |
1657 | 1659 |
1658 int Disassembler::SubstitutePrefetchField(Instruction* instr, | 1660 int DisassemblingDecoder::SubstitutePrefetchField(Instruction* instr, |
1659 const char* format) { | 1661 const char* format) { |
1660 DCHECK(format[0] == 'P'); | 1662 DCHECK(format[0] == 'P'); |
1661 USE(format); | 1663 USE(format); |
1662 | 1664 |
1663 int prefetch_mode = instr->PrefetchMode(); | 1665 int prefetch_mode = instr->PrefetchMode(); |
1664 | 1666 |
1665 const char* ls = (prefetch_mode & 0x10) ? "st" : "ld"; | 1667 const char* ls = (prefetch_mode & 0x10) ? "st" : "ld"; |
1666 int level = (prefetch_mode >> 1) + 1; | 1668 int level = (prefetch_mode >> 1) + 1; |
1667 const char* ks = (prefetch_mode & 1) ? "strm" : "keep"; | 1669 const char* ks = (prefetch_mode & 1) ? "strm" : "keep"; |
1668 | 1670 |
1669 AppendToOutput("p%sl%d%s", ls, level, ks); | 1671 AppendToOutput("p%sl%d%s", ls, level, ks); |
1670 return 6; | 1672 return 6; |
1671 } | 1673 } |
1672 | 1674 |
1673 int Disassembler::SubstituteBarrierField(Instruction* instr, | 1675 int DisassemblingDecoder::SubstituteBarrierField(Instruction* instr, |
1674 const char* format) { | 1676 const char* format) { |
1675 DCHECK(format[0] == 'M'); | 1677 DCHECK(format[0] == 'M'); |
1676 USE(format); | 1678 USE(format); |
1677 | 1679 |
1678 static const char* const options[4][4] = { | 1680 static const char* const options[4][4] = { |
1679 { "sy (0b0000)", "oshld", "oshst", "osh" }, | 1681 { "sy (0b0000)", "oshld", "oshst", "osh" }, |
1680 { "sy (0b0100)", "nshld", "nshst", "nsh" }, | 1682 { "sy (0b0100)", "nshld", "nshst", "nsh" }, |
1681 { "sy (0b1000)", "ishld", "ishst", "ish" }, | 1683 { "sy (0b1000)", "ishld", "ishst", "ish" }, |
1682 { "sy (0b1100)", "ld", "st", "sy" } | 1684 { "sy (0b1100)", "ld", "st", "sy" } |
1683 }; | 1685 }; |
1684 int domain = instr->ImmBarrierDomain(); | 1686 int domain = instr->ImmBarrierDomain(); |
1685 int type = instr->ImmBarrierType(); | 1687 int type = instr->ImmBarrierType(); |
1686 | 1688 |
1687 AppendToOutput("%s", options[domain][type]); | 1689 AppendToOutput("%s", options[domain][type]); |
1688 return 1; | 1690 return 1; |
1689 } | 1691 } |
1690 | 1692 |
1691 | 1693 |
1692 void Disassembler::ResetOutput() { | 1694 void DisassemblingDecoder::ResetOutput() { |
1693 buffer_pos_ = 0; | 1695 buffer_pos_ = 0; |
1694 buffer_[buffer_pos_] = 0; | 1696 buffer_[buffer_pos_] = 0; |
1695 } | 1697 } |
1696 | 1698 |
1697 | 1699 |
1698 void Disassembler::AppendToOutput(const char* format, ...) { | 1700 void DisassemblingDecoder::AppendToOutput(const char* format, ...) { |
1699 va_list args; | 1701 va_list args; |
1700 va_start(args, format); | 1702 va_start(args, format); |
1701 buffer_pos_ += vsnprintf(&buffer_[buffer_pos_], buffer_size_, format, args); | 1703 buffer_pos_ += vsnprintf(&buffer_[buffer_pos_], buffer_size_, format, args); |
1702 va_end(args); | 1704 va_end(args); |
1703 } | 1705 } |
1704 | 1706 |
1705 | 1707 |
1706 void PrintDisassembler::ProcessOutput(Instruction* instr) { | 1708 void PrintDisassembler::ProcessOutput(Instruction* instr) { |
1707 fprintf(stream_, "0x%016" PRIx64 " %08" PRIx32 "\t\t%s\n", | 1709 fprintf(stream_, "0x%016" PRIx64 " %08" PRIx32 "\t\t%s\n", |
1708 reinterpret_cast<uint64_t>(instr), instr->InstructionBits(), | 1710 reinterpret_cast<uint64_t>(instr), instr->InstructionBits(), |
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1754 | 1756 |
1755 const char* NameConverter::NameInCode(byte* addr) const { | 1757 const char* NameConverter::NameInCode(byte* addr) const { |
1756 // The default name converter is called for unknown code, so we will not try | 1758 // The default name converter is called for unknown code, so we will not try |
1757 // to access any memory. | 1759 // to access any memory. |
1758 return ""; | 1760 return ""; |
1759 } | 1761 } |
1760 | 1762 |
1761 | 1763 |
1762 //------------------------------------------------------------------------------ | 1764 //------------------------------------------------------------------------------ |
1763 | 1765 |
1764 class BufferDisassembler : public v8::internal::Disassembler { | 1766 class BufferDisassembler : public v8::internal::DisassemblingDecoder { |
1765 public: | 1767 public: |
1766 explicit BufferDisassembler(v8::internal::Vector<char> out_buffer) | 1768 explicit BufferDisassembler(v8::internal::Vector<char> out_buffer) |
1767 : out_buffer_(out_buffer) { } | 1769 : out_buffer_(out_buffer) { } |
1768 | 1770 |
1769 ~BufferDisassembler() { } | 1771 ~BufferDisassembler() { } |
1770 | 1772 |
1771 virtual void ProcessOutput(v8::internal::Instruction* instr) { | 1773 virtual void ProcessOutput(v8::internal::Instruction* instr) { |
1772 v8::internal::SNPrintF(out_buffer_, "%s", GetOutput()); | 1774 v8::internal::SNPrintF(out_buffer_, "%s", GetOutput()); |
1773 } | 1775 } |
1774 | 1776 |
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1806 decoder.AppendVisitor(&disasm); | 1808 decoder.AppendVisitor(&disasm); |
1807 | 1809 |
1808 for (byte* pc = start; pc < end; pc += v8::internal::kInstructionSize) { | 1810 for (byte* pc = start; pc < end; pc += v8::internal::kInstructionSize) { |
1809 decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(pc)); | 1811 decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(pc)); |
1810 } | 1812 } |
1811 } | 1813 } |
1812 | 1814 |
1813 } // namespace disasm | 1815 } // namespace disasm |
1814 | 1816 |
1815 #endif // V8_TARGET_ARCH_ARM64 | 1817 #endif // V8_TARGET_ARCH_ARM64 |
OLD | NEW |