Add new form of ldr/str (immediate) to ARM integrated assembler.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 519 matching lines @@
   InstARM32LoadBase(const InstARM32LoadBase &) = delete;
   InstARM32LoadBase &operator=(const InstARM32LoadBase &) = delete;
 
 public:
   static InstARM32LoadBase *create(Cfg *Func, Variable *Dest, Operand *Source,
                                    CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32LoadBase>())
         InstARM32LoadBase(Func, Dest, Source, Predicate);
   }
   void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << " ";
     dumpDest(Func);
     Str << ", ";
     dumpSources(Func);
   }
@@ skipping 450 matching lines @@
   InstARM32Str &operator=(const InstARM32Str &) = delete;
 
 public:
   /// Value must be a register.
   static InstARM32Str *create(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                               CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32Str>())
         InstARM32Str(Func, Value, Mem, Predicate);
   }
   void emit(const Cfg *Func) const override;
+  void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override;
   static bool classof(const Inst *Inst) { return isClassof(Inst, Str); }
 
 private:
   InstARM32Str(Cfg *Func, Variable *Value, OperandARM32Mem *Mem,
                CondARM32::Cond Predicate);
 };
 
 /// Exclusive Store instruction. Like its non-exclusive sibling, it's important
 /// for liveness that there is no Dest operand (OperandARM32Mem instead of Dest
@@ skipping 209 matching lines @@
 // default implementations. Without this, there is the possibility of ODR
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H