Add new form of ldr/str (immediate) to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 76 matching lines @@
 // Mask to pull out PC offset from branch (b) instruction.
 static constexpr int kBranchOffsetBits = 24;
 static constexpr IOffsetT kBranchOffsetMask = 0x00ffffff;
 
 inline IValueT encodeBool(bool B) { return B ? 1 : 0; }
 
 inline IValueT encodeGPRRegister(RegARM32::GPRRegister Rn) {
   return static_cast<IValueT>(Rn);
 }
 
+inline RegARM32::GPRRegister decodeGPRRegister(IValueT R) {
+  return static_cast<RegARM32::GPRRegister>(R);
+}
+
 inline bool isGPRRegisterDefined(RegARM32::GPRRegister R) {
   return R != RegARM32::Encoded_Not_GPR;
 }
 
 inline bool isGPRRegisterDefined(IValueT R) {
   return R != encodeGPRRegister(RegARM32::Encoded_Not_GPR);
 }
 
 inline bool isConditionDefined(CondARM32::Cond Cond) {
   return Cond != CondARM32::kNone;
@@ skipping 24 matching lines @@
   return (Value >> Shift) & ((1 << Bits) - 1);
 }
 
 // Extract out a Bit in Value.
 inline bool isBitSet(IValueT Bit, IValueT Value) {
   return (Value & Bit) == Bit;
 }
 
 // Returns the GPR register at given Shift in Value.
 inline RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
-  return static_cast<RegARM32::GPRRegister>((Value >> Shift) & 0xF);
+  return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
 // The way an operand was decoded in functions decodeOperand and decodeAddress
 // below.
 enum DecodedResult {
   // Unable to decode, value left undefined.
   CantDecode = 0,
   // Value is register found.
   DecodedAsRegister,
   // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
   // value.
   DecodedAsRotatedImm8,
   // i.e. 0000000pu0w0nnnn0000iiiiiiiiiiii where nnnn is the base register Rn,
   // p=1 if pre-indexed addressing, u=1 if offset positive, w=1 if writeback to
   // Rn should be used, and iiiiiiiiiiii is the offset.
   DecodedAsImmRegOffset
 };
 
 // Encodes iiiiitt0mmmm for data-processing (2nd) operands where iiiii=Imm5,
 // tt=Shift, and mmmm=Rm.
 IValueT encodeShiftRotateImm5(IValueT Rm, OperandARM32::ShiftKind Shift,
-                              IValueT imm5) {
+                              IOffsetT imm5) {
   (void)kShiftImmBits;
   assert(imm5 < (1 << kShiftImmBits));
   return (imm5 << kShiftImmShift) | (encodeShift(Shift) << kShiftShift) | Rm;
 }
 
 DecodedResult decodeOperand(const Operand *Opnd, IValueT &Value) {
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
       Value = Var->getRegNum();
       return DecodedAsRegister;
@@ skipping 27 matching lines @@
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantDecode;
     const IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantDecode;
     Value = decodeImmRegOffset(RegARM32::Encoded_Reg_sp, Offset,
                                OperandARM32Mem::Offset);
     return DecodedAsImmRegOffset;
   }
+  if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
+    if (Mem->isRegReg())
+      // TODO(kschimpf) Add this case.
+      return CantDecode;
+    Variable *Var = Mem->getBase();
+    if (!Var->hasReg())
+      return CantDecode;
+    ConstantInteger32 *Offset = Mem->getOffset();
+    Value = decodeImmRegOffset(decodeGPRRegister(Var->getRegNum()),
+                               Offset->getValue(), Mem->getAddrMode());
+    return DecodedAsImmRegOffset;
+  }
   return CantDecode;
 }
 
 // Checks that Offset can fit in imm24 constant of branch (b) instruction.
 bool canEncodeBranchOffset(IOffsetT Offset) {
   return Utils::IsAligned(Offset, 4) &&
          Utils::IsInt(kBranchOffsetBits, Offset >> 2);
 }
 
 } // end of anonymous namespace
@@ skipping 430 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice