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1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// | 1 //===- subzero/src/IceAssemblerARM32.h - Assembler for ARM32 ----*- C++ -*-===// |
2 // | 2 // |
3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 3 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
4 // for details. All rights reserved. Use of this source code is governed by a | 4 // for details. All rights reserved. Use of this source code is governed by a |
5 // BSD-style license that can be found in the LICENSE file. | 5 // BSD-style license that can be found in the LICENSE file. |
6 // | 6 // |
7 // Modified by the Subzero authors. | 7 // Modified by the Subzero authors. |
8 // | 8 // |
9 //===----------------------------------------------------------------------===// | 9 //===----------------------------------------------------------------------===// |
10 // | 10 // |
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139 bool SetFlags, CondARM32::Cond Cond); | 139 bool SetFlags, CondARM32::Cond Cond); |
140 | 140 |
141 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 141 void add(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
142 bool SetFlags, CondARM32::Cond Cond); | 142 bool SetFlags, CondARM32::Cond Cond); |
143 | 143 |
144 void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 144 void and_(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
145 bool SetFlags, CondARM32::Cond Cond); | 145 bool SetFlags, CondARM32::Cond Cond); |
146 | 146 |
147 void b(Label *L, CondARM32::Cond Cond); | 147 void b(Label *L, CondARM32::Cond Cond); |
148 | 148 |
| 149 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); |
| 150 |
149 void bkpt(uint16_t Imm16); | 151 void bkpt(uint16_t Imm16); |
150 | 152 |
151 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); | 153 void ldr(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); |
152 | 154 |
153 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); | 155 void mov(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
154 | 156 |
| 157 void mul(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
| 158 bool SetFlags, CondARM32::Cond Cond); |
| 159 |
155 void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); | 160 void movw(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
156 | 161 |
157 void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); | 162 void movt(const Operand *OpRd, const Operand *OpSrc, CondARM32::Cond Cond); |
158 | 163 |
159 void bx(RegARM32::GPRRegister Rm, CondARM32::Cond Cond = CondARM32::AL); | |
160 | |
161 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 164 void sbc(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
162 bool SetFlags, CondARM32::Cond Cond); | 165 bool SetFlags, CondARM32::Cond Cond); |
163 | 166 |
164 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); | 167 void str(const Operand *OpRt, const Operand *OpAddress, CondARM32::Cond Cond); |
165 | 168 |
166 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, | 169 void sub(const Operand *OpRd, const Operand *OpRn, const Operand *OpSrc1, |
167 bool SetFlags, CondARM32::Cond Cond); | 170 bool SetFlags, CondARM32::Cond Cond); |
168 | 171 |
169 static bool classof(const Assembler *Asm) { | 172 static bool classof(const Assembler *Asm) { |
170 return Asm->getKind() == Asm_ARM32; | 173 return Asm->getKind() == Asm_ARM32; |
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192 | 195 |
193 void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link); | 196 void emitType05(CondARM32::Cond COnd, int32_t Offset, bool Link); |
194 | 197 |
195 // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType, | 198 // Pattern ccccoooaabalnnnnttttaaaaaaaaaaaa where cccc=Cond, ooo=InstType, |
196 // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that | 199 // l=isLoad, b=isByte, and aaa0a0aaaa0000aaaaaaaaaaaa=Address. Note that |
197 // Address is assumed to be defined by decodeAddress() in | 200 // Address is assumed to be defined by decodeAddress() in |
198 // IceAssemblerARM32.cpp. | 201 // IceAssemblerARM32.cpp. |
199 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad, | 202 void emitMemOp(CondARM32::Cond Cond, IValueT InstType, bool IsLoad, |
200 bool IsByte, uint32_t Rt, uint32_t Address); | 203 bool IsByte, uint32_t Rt, uint32_t Address); |
201 | 204 |
| 205 // Pattern ccccxxxxxxxfnnnnddddssss1001mmmm where cccc=Cond, dddd=Rd, nnnn=Rn, |
| 206 // mmmm=Rm, ssss=Rs, f=SetCc, and xxxxxxx=Opcode. |
| 207 void emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, IValueT Rn, |
| 208 IValueT Rm, IValueT Rs, bool SetCc); |
| 209 |
202 void emitBranch(Label *L, CondARM32::Cond, bool Link); | 210 void emitBranch(Label *L, CondARM32::Cond, bool Link); |
203 | 211 |
204 // Encodes the given Offset into the branch instruction Inst. | 212 // Encodes the given Offset into the branch instruction Inst. |
205 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); | 213 IValueT encodeBranchOffset(IOffsetT Offset, IValueT Inst); |
206 | 214 |
207 // Returns the offset encoded in the branch instruction Inst. | 215 // Returns the offset encoded in the branch instruction Inst. |
208 static IOffsetT decodeBranchOffset(IValueT Inst); | 216 static IOffsetT decodeBranchOffset(IValueT Inst); |
209 }; | 217 }; |
210 | 218 |
211 } // end of namespace ARM32 | 219 } // end of namespace ARM32 |
212 } // end of namespace Ice | 220 } // end of namespace Ice |
213 | 221 |
214 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H | 222 #endif // SUBZERO_SRC_ICEASSEMBLERARM32_H |
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