Add mul instruction to ARM integrated assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 19 matching lines @@
 using namespace Ice::ARM32;
 
 // The following define individual bits.
 static constexpr IValueT B0 = 1;
 static constexpr IValueT B1 = 1 << 1;
 static constexpr IValueT B2 = 1 << 2;
 static constexpr IValueT B3 = 1 << 3;
 static constexpr IValueT B4 = 1 << 4;
 static constexpr IValueT B5 = 1 << 5;
 static constexpr IValueT B6 = 1 << 6;
+static constexpr IValueT B7 = 1 << 7;
 static constexpr IValueT B21 = 1 << 21;
 static constexpr IValueT B22 = 1 << 22;
 static constexpr IValueT B24 = 1 << 24;
 static constexpr IValueT B25 = 1 << 25;
 
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on ARM section A5.1.
 static constexpr IValueT L = 1 << 20; // load (or store)
 static constexpr IValueT W = 1 << 21; // writeback base register
                                       // (or leave unchanged)
 static constexpr IValueT B = 1 << 22; // unsigned byte (or word)
 static constexpr IValueT U = 1 << 23; // positive (or negative)
                                       // offset/index
 static constexpr IValueT P = 1 << 24; // offset/pre-indexed
                                       // addressing (or
                                       // post-indexed addressing)
 
 static constexpr IValueT kConditionShift = 28;
 static constexpr IValueT kLinkShift = 24;
 static constexpr IValueT kOpcodeShift = 21;
 static constexpr IValueT kRdShift = 12;
 static constexpr IValueT kRmShift = 0;
 static constexpr IValueT kRnShift = 16;
+static constexpr IValueT kRsShift = 8;
 static constexpr IValueT kSShift = 20;
 static constexpr IValueT kTypeShift = 25;
 
 // Immediate instruction fields encoding.
 static constexpr IValueT kImmed8Bits = 8;
 static constexpr IValueT kImmed8Shift = 0;
 static constexpr IValueT kRotateBits = 4;
 static constexpr IValueT kRotateShift = 8;
 
 // Shift instruction register fields encodings.
@@ skipping 296 matching lines @@
                                IValueT Address) {
   if (!isGPRRegisterDefined(Rt) || !isConditionDefined(Cond))
     return setNeedsTextFixup();
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
                            (InstType << kTypeShift) | (IsLoad ? L : 0) |
                            (IsByte ? B : 0) | (Rt << kRdShift) | Address;
   emitInst(Encoding);
 }
 
+void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd,
+                               IValueT Rn, IValueT Rm, IValueT Rs, bool SetCc) {
+  if (!isGPRRegisterDefined(Rd) || !isGPRRegisterDefined(Rn) ||
+      !isGPRRegisterDefined(Rm) || !isGPRRegisterDefined(Rs) ||
+      !isConditionDefined(Cond))
+    return setNeedsTextFixup();
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
+                     (encodeBool(SetCc) << kSShift) | (Rn << kRnShift) |
+                     (Rd << kRdShift) | (Rs << kRsShift) | B7 | B4 |
+                     (Rm << kRmShift);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::adc(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   constexpr IValueT Adc = B2 | B0; // 0101
@@ skipping 340 matching lines @@
     return setNeedsTextFixup();
   if (!isBitSet(P, Address) && isBitSet(W, Address))
     return setNeedsTextFixup();
   if (!IsByte && (getGPRReg(kRnShift, Address) == RegARM32::Encoded_Reg_sp) &&
       isBitSet(P, Address) && !isBitSet(U, Address) && isBitSet(W, Address) &&
       (mask(Address, kImm12Shift, kImmed12Bits) == 0x8 /* 000000000100 */))
     return setNeedsTextFixup();
   emitMemOp(Cond, kInstTypeMemImmediate, IsLoad, IsByte, Rt, Address);
 }
 
+void AssemblerARM32::mul(const Operand *OpRd, const Operand *OpRn,
+                         const Operand *OpSrc1, bool SetFlags,
+                         CondARM32::Cond Cond) {
+  IValueT Rd;
+  if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rn;
+  if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  IValueT Rm;
+  if (decodeOperand(OpSrc1, Rm) != DecodedAsRegister)
+    return setNeedsTextFixup();
+  // MUL - ARM section A8.8.114, encoding A1.
+  //   mul{s}<c> <Rd>, <Rn>, <Rm>
+  //
+  // cccc0000000sdddd0000mmmm1001nnnn where cccc=Cond, dddd=Rd, nnnn=Rn,
+  // mmmm=Rm, and s=SetFlags.
+  if (Rd == RegARM32::Encoded_Reg_pc || Rn == RegARM32::Encoded_Reg_pc ||
+      Rm == RegARM32::Encoded_Reg_pc)
+    llvm::report_fatal_error("Mul instruction unpredictable on pc");
+  // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
+  constexpr IValueT MulOpcode = 0;
+  emitMulOp(Cond, MulOpcode, RegARM32::Encoded_Reg_r0, Rd, Rn, Rm, SetFlags);
+}
+
 void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
                          const Operand *OpSrc1, bool SetFlags,
                          CondARM32::Cond Cond) {
   IValueT Rd;
   if (decodeOperand(OpRd, Rd) != DecodedAsRegister)
     return setNeedsTextFixup();
   IValueT Rn;
   if (decodeOperand(OpRn, Rn) != DecodedAsRegister)
     return setNeedsTextFixup();
   constexpr IValueT Sub = B1; // 0010
@@ skipping 29 matching lines @@
       // Conditions of rule violated.
       return setNeedsTextFixup();
     emitType01(Cond, kInstTypeDataImmediate, Sub, SetFlags, Rn, Rd, Src1Value);
     return;
   }
   }
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice