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Side by Side Diff: src/DartARM32/assembler_arm.h

Issue 1430713003: Add mul instruction to ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 5 years, 1 month ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #ifndef VM_ASSEMBLER_ARM_H_ 9 #ifndef VM_ASSEMBLER_ARM_H_
10 #define VM_ASSEMBLER_ARM_H_ 10 #define VM_ASSEMBLER_ARM_H_
(...skipping 482 matching lines...) Expand 10 before | Expand all | Expand 10 after
493 void bic(Register rd, Register rn, Operand o, Condition cond = AL); 493 void bic(Register rd, Register rn, Operand o, Condition cond = AL);
494 void bics(Register rd, Register rn, Operand o, Condition cond = AL); 494 void bics(Register rd, Register rn, Operand o, Condition cond = AL);
495 495
496 void mvn(Register rd, Operand o, Condition cond = AL); 496 void mvn(Register rd, Operand o, Condition cond = AL);
497 void mvns(Register rd, Operand o, Condition cond = AL); 497 void mvns(Register rd, Operand o, Condition cond = AL);
498 498
499 // Miscellaneous data-processing instructions. 499 // Miscellaneous data-processing instructions.
500 void clz(Register rd, Register rm, Condition cond = AL); 500 void clz(Register rd, Register rm, Condition cond = AL);
501 501
502 // Multiply instructions. 502 // Multiply instructions.
503 #if 0
504 // Moved to AssemblerARM32::mul()
503 void mul(Register rd, Register rn, Register rm, Condition cond = AL); 505 void mul(Register rd, Register rn, Register rm, Condition cond = AL);
504 void muls(Register rd, Register rn, Register rm, Condition cond = AL); 506 void muls(Register rd, Register rn, Register rm, Condition cond = AL);
507 #endif
505 void mla(Register rd, Register rn, Register rm, Register ra, 508 void mla(Register rd, Register rn, Register rm, Register ra,
506 Condition cond = AL); 509 Condition cond = AL);
507 void mls(Register rd, Register rn, Register rm, Register ra, 510 void mls(Register rd, Register rn, Register rm, Register ra,
508 Condition cond = AL); 511 Condition cond = AL);
509 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm, 512 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
510 Condition cond = AL); 513 Condition cond = AL);
511 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm, 514 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm,
512 Condition cond = AL); 515 Condition cond = AL);
513 void smlal(Register rd_lo, Register rd_hi, Register rn, Register rm, 516 void smlal(Register rd_lo, Register rd_hi, Register rn, Register rm,
514 Condition cond = AL); 517 Condition cond = AL);
(...skipping 638 matching lines...) Expand 10 before | Expand all | Expand 10 after
1153 Register rd, 1156 Register rd,
1154 Register rm, 1157 Register rm,
1155 Operand o); 1158 Operand o);
1156 1159
1157 void EmitShiftRegister(Condition cond, 1160 void EmitShiftRegister(Condition cond,
1158 Shift opcode, 1161 Shift opcode,
1159 Register rd, 1162 Register rd,
1160 Register rm, 1163 Register rm,
1161 Operand o); 1164 Operand o);
1162 1165
1166 #if 0
1167 // Moved to ARM32::AssemblerARM32::emitMulOp()
1163 void EmitMulOp(Condition cond, 1168 void EmitMulOp(Condition cond,
1164 int32_t opcode, 1169 int32_t opcode,
1165 Register rd, 1170 Register rd,
1166 Register rn, 1171 Register rn,
1167 Register rm, 1172 Register rm,
1168 Register rs); 1173 Register rs);
1174 #endif
1169 1175
1170 void EmitDivOp(Condition cond, 1176 void EmitDivOp(Condition cond,
1171 int32_t opcode, 1177 int32_t opcode,
1172 Register rd, 1178 Register rd,
1173 Register rn, 1179 Register rn,
1174 Register rm); 1180 Register rm);
1175 1181
1176 void EmitMultiVSMemOp(Condition cond, 1182 void EmitMultiVSMemOp(Condition cond,
1177 BlockAddressMode am, 1183 BlockAddressMode am,
1178 bool load, 1184 bool load,
(...skipping 74 matching lines...) Expand 10 before | Expand all | Expand 10 after
1253 Register new_value, 1259 Register new_value,
1254 FieldContent old_content); 1260 FieldContent old_content);
1255 1261
1256 DISALLOW_ALLOCATION(); 1262 DISALLOW_ALLOCATION();
1257 DISALLOW_COPY_AND_ASSIGN(Assembler); 1263 DISALLOW_COPY_AND_ASSIGN(Assembler);
1258 }; 1264 };
1259 1265
1260 } // namespace dart 1266 } // namespace dart
1261 1267
1262 #endif // VM_ASSEMBLER_ARM_H_ 1268 #endif // VM_ASSEMBLER_ARM_H_
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