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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 // | 4 // |
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
8 | 8 |
9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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346 // Moved to ARM::AssemblerARM32::movt | 346 // Moved to ARM::AssemblerARM32::movt |
347 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) { | 347 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) { |
348 ASSERT(cond != kNoCondition); | 348 ASSERT(cond != kNoCondition); |
349 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | | 349 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
350 B25 | B24 | B22 | ((imm16 >> 12) << 16) | | 350 B25 | B24 | B22 | ((imm16 >> 12) << 16) | |
351 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); | 351 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); |
352 Emit(encoding); | 352 Emit(encoding); |
353 } | 353 } |
354 #endif | 354 #endif |
355 | 355 |
356 | 356 #if 0 |
| 357 // Moved to ARM32::AssemblerARM32::emitMulOp |
357 void Assembler::EmitMulOp(Condition cond, int32_t opcode, | 358 void Assembler::EmitMulOp(Condition cond, int32_t opcode, |
358 Register rd, Register rn, | 359 Register rd, Register rn, |
359 Register rm, Register rs) { | 360 Register rm, Register rs) { |
360 ASSERT(rd != kNoRegister); | 361 ASSERT(rd != kNoRegister); |
361 ASSERT(rn != kNoRegister); | 362 ASSERT(rn != kNoRegister); |
362 ASSERT(rm != kNoRegister); | 363 ASSERT(rm != kNoRegister); |
363 ASSERT(rs != kNoRegister); | 364 ASSERT(rs != kNoRegister); |
364 ASSERT(cond != kNoCondition); | 365 ASSERT(cond != kNoCondition); |
365 int32_t encoding = opcode | | 366 int32_t encoding = opcode | |
366 (static_cast<int32_t>(cond) << kConditionShift) | | 367 (static_cast<int32_t>(cond) << kConditionShift) | |
367 (static_cast<int32_t>(rn) << kRnShift) | | 368 (static_cast<int32_t>(rn) << kRnShift) | |
368 (static_cast<int32_t>(rd) << kRdShift) | | 369 (static_cast<int32_t>(rd) << kRdShift) | |
369 (static_cast<int32_t>(rs) << kRsShift) | | 370 (static_cast<int32_t>(rs) << kRsShift) | |
370 B7 | B4 | | 371 B7 | B4 | |
371 (static_cast<int32_t>(rm) << kRmShift); | 372 (static_cast<int32_t>(rm) << kRmShift); |
372 Emit(encoding); | 373 Emit(encoding); |
373 } | 374 } |
374 | 375 |
375 | 376 // Moved to ARM32::AssemblerARM32::mul |
376 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { | 377 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { |
377 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. | 378 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. |
378 EmitMulOp(cond, 0, R0, rd, rn, rm); | 379 EmitMulOp(cond, 0, R0, rd, rn, rm); |
379 } | 380 } |
380 | 381 #endif |
381 | 382 |
382 // Like mul, but sets condition flags. | 383 // Like mul, but sets condition flags. |
383 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) { | 384 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) { |
384 EmitMulOp(cond, B20, R0, rd, rn, rm); | 385 EmitMulOp(cond, B20, R0, rd, rn, rm); |
385 } | 386 } |
386 | 387 |
387 | 388 |
388 void Assembler::mla(Register rd, Register rn, | 389 void Assembler::mla(Register rd, Register rn, |
389 Register rm, Register ra, Condition cond) { | 390 Register rm, Register ra, Condition cond) { |
390 // rd <- ra + rn * rm. | 391 // rd <- ra + rn * rm. |
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3673 | 3674 |
3674 | 3675 |
3675 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3676 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3676 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3677 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3677 return fpu_reg_names[reg]; | 3678 return fpu_reg_names[reg]; |
3678 } | 3679 } |
3679 | 3680 |
3680 } // namespace dart | 3681 } // namespace dart |
3681 | 3682 |
3682 #endif // defined TARGET_ARCH_ARM | 3683 #endif // defined TARGET_ARCH_ARM |
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