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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 340 | 340 |
| 341 | 341 |
| 342 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) { | 342 void Assembler::movt(Register rd, uint16_t imm16, Condition cond) { |
| 343 ASSERT(cond != kNoCondition); | 343 ASSERT(cond != kNoCondition); |
| 344 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | | 344 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | |
| 345 B25 | B24 | B22 | ((imm16 >> 12) << 16) | | 345 B25 | B24 | B22 | ((imm16 >> 12) << 16) | |
| 346 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); | 346 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff); |
| 347 Emit(encoding); | 347 Emit(encoding); |
| 348 } | 348 } |
| 349 | 349 |
| 350 | 350 #if 0 |
| 351 // Moved to ARM32::AssemblerARM32::emitMulOp |
| 351 void Assembler::EmitMulOp(Condition cond, int32_t opcode, | 352 void Assembler::EmitMulOp(Condition cond, int32_t opcode, |
| 352 Register rd, Register rn, | 353 Register rd, Register rn, |
| 353 Register rm, Register rs) { | 354 Register rm, Register rs) { |
| 354 ASSERT(rd != kNoRegister); | 355 ASSERT(rd != kNoRegister); |
| 355 ASSERT(rn != kNoRegister); | 356 ASSERT(rn != kNoRegister); |
| 356 ASSERT(rm != kNoRegister); | 357 ASSERT(rm != kNoRegister); |
| 357 ASSERT(rs != kNoRegister); | 358 ASSERT(rs != kNoRegister); |
| 358 ASSERT(cond != kNoCondition); | 359 ASSERT(cond != kNoCondition); |
| 359 int32_t encoding = opcode | | 360 int32_t encoding = opcode | |
| 360 (static_cast<int32_t>(cond) << kConditionShift) | | 361 (static_cast<int32_t>(cond) << kConditionShift) | |
| 361 (static_cast<int32_t>(rn) << kRnShift) | | 362 (static_cast<int32_t>(rn) << kRnShift) | |
| 362 (static_cast<int32_t>(rd) << kRdShift) | | 363 (static_cast<int32_t>(rd) << kRdShift) | |
| 363 (static_cast<int32_t>(rs) << kRsShift) | | 364 (static_cast<int32_t>(rs) << kRsShift) | |
| 364 B7 | B4 | | 365 B7 | B4 | |
| 365 (static_cast<int32_t>(rm) << kRmShift); | 366 (static_cast<int32_t>(rm) << kRmShift); |
| 366 Emit(encoding); | 367 Emit(encoding); |
| 367 } | 368 } |
| 368 | 369 |
| 369 | 370 // Moved to ARM32::AssemblerARM32::mul |
| 370 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { | 371 void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { |
| 371 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. | 372 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. |
| 372 EmitMulOp(cond, 0, R0, rd, rn, rm); | 373 EmitMulOp(cond, 0, R0, rd, rn, rm); |
| 373 } | 374 } |
| 374 | 375 #endif |
| 375 | 376 |
| 376 // Like mul, but sets condition flags. | 377 // Like mul, but sets condition flags. |
| 377 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) { | 378 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) { |
| 378 EmitMulOp(cond, B20, R0, rd, rn, rm); | 379 EmitMulOp(cond, B20, R0, rd, rn, rm); |
| 379 } | 380 } |
| 380 | 381 |
| 381 | 382 |
| 382 void Assembler::mla(Register rd, Register rn, | 383 void Assembler::mla(Register rd, Register rn, |
| 383 Register rm, Register ra, Condition cond) { | 384 Register rm, Register ra, Condition cond) { |
| 384 // rd <- ra + rn * rm. | 385 // rd <- ra + rn * rm. |
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| 3667 | 3668 |
| 3668 | 3669 |
| 3669 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3670 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3670 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3671 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3671 return fpu_reg_names[reg]; | 3672 return fpu_reg_names[reg]; |
| 3672 } | 3673 } |
| 3673 | 3674 |
| 3674 } // namespace dart | 3675 } // namespace dart |
| 3675 | 3676 |
| 3676 #endif // defined TARGET_ARCH_ARM | 3677 #endif // defined TARGET_ARCH_ARM |
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