Add MLA instruction to ARM integerated assembler.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 373 matching lines @@
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 #endif
 
 // Like mul, but sets condition flags.
 void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
   EmitMulOp(cond, B20, R0, rd, rn, rm);
 }
 
-
+#if 0
+// Moved to ARM32::AssemblerARM32::mla
 void Assembler::mla(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra + rn * rm.
   // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
   EmitMulOp(cond, B21, ra, rd, rn, rm);
 }
+#endif
 
 
 void Assembler::mls(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra - rn * rm.
   if (TargetCPUFeatures::arm_version() == ARMv7) {
     // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
     EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
@@ skipping 3270 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM