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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #ifndef VM_ASSEMBLER_ARM_H_ | 9 #ifndef VM_ASSEMBLER_ARM_H_ |
| 10 #define VM_ASSEMBLER_ARM_H_ | 10 #define VM_ASSEMBLER_ARM_H_ |
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| 496 void bics(Register rd, Register rn, Operand o, Condition cond = AL); | 496 void bics(Register rd, Register rn, Operand o, Condition cond = AL); |
| 497 | 497 |
| 498 void mvn(Register rd, Operand o, Condition cond = AL); | 498 void mvn(Register rd, Operand o, Condition cond = AL); |
| 499 void mvns(Register rd, Operand o, Condition cond = AL); | 499 void mvns(Register rd, Operand o, Condition cond = AL); |
| 500 | 500 |
| 501 // Miscellaneous data-processing instructions. | 501 // Miscellaneous data-processing instructions. |
| 502 void clz(Register rd, Register rm, Condition cond = AL); | 502 void clz(Register rd, Register rm, Condition cond = AL); |
| 503 | 503 |
| 504 // Multiply instructions. | 504 // Multiply instructions. |
| 505 #if 0 | 505 #if 0 |
| 506 // Moved to AssemblerARM32::mul() | 506 // Moved to ARM32::AssemblerARM32::mul() |
| 507 void mul(Register rd, Register rn, Register rm, Condition cond = AL); | 507 void mul(Register rd, Register rn, Register rm, Condition cond = AL); |
| 508 void muls(Register rd, Register rn, Register rm, Condition cond = AL); | 508 void muls(Register rd, Register rn, Register rm, Condition cond = AL); |
| 509 #endif | 509 #endif |
| 510 void mla(Register rd, Register rn, Register rm, Register ra, | 510 void mla(Register rd, Register rn, Register rm, Register ra, |
| 511 Condition cond = AL); | 511 Condition cond = AL); |
| 512 void mls(Register rd, Register rn, Register rm, Register ra, | 512 void mls(Register rd, Register rn, Register rm, Register ra, |
| 513 Condition cond = AL); | 513 Condition cond = AL); |
| 514 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm, | 514 void smull(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 515 Condition cond = AL); | 515 Condition cond = AL); |
| 516 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm, | 516 void umull(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 517 Condition cond = AL); | 517 Condition cond = AL); |
| 518 void smlal(Register rd_lo, Register rd_hi, Register rn, Register rm, | 518 void smlal(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 519 Condition cond = AL); | 519 Condition cond = AL); |
| 520 void umlal(Register rd_lo, Register rd_hi, Register rn, Register rm, | 520 void umlal(Register rd_lo, Register rd_hi, Register rn, Register rm, |
| 521 Condition cond = AL); | 521 Condition cond = AL); |
| 522 | 522 |
| 523 // Emulation of this instruction uses IP and the condition codes. Therefore, | 523 // Emulation of this instruction uses IP and the condition codes. Therefore, |
| 524 // none of the registers can be IP, and the instruction can only be used | 524 // none of the registers can be IP, and the instruction can only be used |
| 525 // unconditionally. | 525 // unconditionally. |
| 526 void umaal(Register rd_lo, Register rd_hi, Register rn, Register rm); | 526 void umaal(Register rd_lo, Register rd_hi, Register rn, Register rm); |
| 527 | 527 |
| 528 // Division instructions. | 528 // Division instructions. |
| 529 #if 0 |
| 530 // Moved to ARM32::AssemblerARM32::sdiv() |
| 529 void sdiv(Register rd, Register rn, Register rm, Condition cond = AL); | 531 void sdiv(Register rd, Register rn, Register rm, Condition cond = AL); |
| 532 #endif |
| 530 void udiv(Register rd, Register rn, Register rm, Condition cond = AL); | 533 void udiv(Register rd, Register rn, Register rm, Condition cond = AL); |
| 531 | 534 |
| 532 #if 0 | 535 #if 0 |
| 533 // Moved to AssemblerARM32::ldr() | 536 // Moved to ARM32::AssemblerARM32::ldr() |
| 534 // Load/store instructions. | 537 // Load/store instructions. |
| 535 void ldr(Register rd, Address ad, Condition cond = AL); | 538 void ldr(Register rd, Address ad, Condition cond = AL); |
| 536 // Moved to AssemblerARM32::str() | 539 // Moved to ARM32::AssemblerARM32::str() |
| 537 void str(Register rd, Address ad, Condition cond = AL); | 540 void str(Register rd, Address ad, Condition cond = AL); |
| 538 | 541 |
| 539 // Moved to AssemblerARM32::ldr() | 542 // Moved to ARM32::AssemblerARM32::ldr() |
| 540 void ldrb(Register rd, Address ad, Condition cond = AL); | 543 void ldrb(Register rd, Address ad, Condition cond = AL); |
| 541 // Moved to AssemblerARM32::str() | 544 // Moved to ARM32::AssemblerARM32::str() |
| 542 void strb(Register rd, Address ad, Condition cond = AL); | 545 void strb(Register rd, Address ad, Condition cond = AL); |
| 543 #endif | 546 #endif |
| 544 | 547 |
| 545 void ldrh(Register rd, Address ad, Condition cond = AL); | 548 void ldrh(Register rd, Address ad, Condition cond = AL); |
| 546 void strh(Register rd, Address ad, Condition cond = AL); | 549 void strh(Register rd, Address ad, Condition cond = AL); |
| 547 | 550 |
| 548 void ldrsb(Register rd, Address ad, Condition cond = AL); | 551 void ldrsb(Register rd, Address ad, Condition cond = AL); |
| 549 void ldrsh(Register rd, Address ad, Condition cond = AL); | 552 void ldrsh(Register rd, Address ad, Condition cond = AL); |
| 550 | 553 |
| 551 // ldrd and strd actually support the full range of addressing modes, but | 554 // ldrd and strd actually support the full range of addressing modes, but |
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| 1166 Operand o); | 1169 Operand o); |
| 1167 | 1170 |
| 1168 #if 0 | 1171 #if 0 |
| 1169 // Moved to ARM32::AssemblerARM32::emitMulOp() | 1172 // Moved to ARM32::AssemblerARM32::emitMulOp() |
| 1170 void EmitMulOp(Condition cond, | 1173 void EmitMulOp(Condition cond, |
| 1171 int32_t opcode, | 1174 int32_t opcode, |
| 1172 Register rd, | 1175 Register rd, |
| 1173 Register rn, | 1176 Register rn, |
| 1174 Register rm, | 1177 Register rm, |
| 1175 Register rs); | 1178 Register rs); |
| 1176 #endif | |
| 1177 | 1179 |
| 1180 // Moved to ARM32::AssemblerAR32::emitDivOp(); |
| 1178 void EmitDivOp(Condition cond, | 1181 void EmitDivOp(Condition cond, |
| 1179 int32_t opcode, | 1182 int32_t opcode, |
| 1180 Register rd, | 1183 Register rd, |
| 1181 Register rn, | 1184 Register rn, |
| 1182 Register rm); | 1185 Register rm); |
| 1186 #endif |
| 1183 | 1187 |
| 1184 void EmitMultiVSMemOp(Condition cond, | 1188 void EmitMultiVSMemOp(Condition cond, |
| 1185 BlockAddressMode am, | 1189 BlockAddressMode am, |
| 1186 bool load, | 1190 bool load, |
| 1187 Register base, | 1191 Register base, |
| 1188 SRegister start, | 1192 SRegister start, |
| 1189 uint32_t count); | 1193 uint32_t count); |
| 1190 | 1194 |
| 1191 void EmitMultiVDMemOp(Condition cond, | 1195 void EmitMultiVDMemOp(Condition cond, |
| 1192 BlockAddressMode am, | 1196 BlockAddressMode am, |
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| 1261 Register new_value, | 1265 Register new_value, |
| 1262 FieldContent old_content); | 1266 FieldContent old_content); |
| 1263 | 1267 |
| 1264 DISALLOW_ALLOCATION(); | 1268 DISALLOW_ALLOCATION(); |
| 1265 DISALLOW_COPY_AND_ASSIGN(Assembler); | 1269 DISALLOW_COPY_AND_ASSIGN(Assembler); |
| 1266 }; | 1270 }; |
| 1267 | 1271 |
| 1268 } // namespace dart | 1272 } // namespace dart |
| 1269 | 1273 |
| 1270 #endif // VM_ASSEMBLER_ARM_H_ | 1274 #endif // VM_ASSEMBLER_ARM_H_ |
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