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Side by Side Diff: unittest/AssemblerX8632/GPRArith.cpp

Issue 1428443002: Enhance address mode recovery (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Streamline absolute addressing support (rip-relative on x64) Created 5 years, 1 month ago
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1 //===- subzero/unittest/AssemblerX8632/GPRArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8632/GPRArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 108 matching lines...) Expand 10 before | Expand all | Expand 10 after
119 TestSetCC(le, ebx, 0x1u, ecx, 0x80000000u, edx, 0u); 119 TestSetCC(le, ebx, 0x1u, ecx, 0x80000000u, edx, 0u);
120 120
121 #undef TestSetCC 121 #undef TestSetCC
122 } 122 }
123 123
124 TEST_F(AssemblerX8632Test, Lea) { 124 TEST_F(AssemblerX8632Test, Lea) {
125 #define TestLeaBaseDisp(Base, BaseValue, Disp, Dst) \ 125 #define TestLeaBaseDisp(Base, BaseValue, Disp, Dst) \
126 do { \ 126 do { \
127 static constexpr char TestString[] = \ 127 static constexpr char TestString[] = \
128 "(" #Base ", " #BaseValue ", " #Dst ")"; \ 128 "(" #Base ", " #BaseValue ", " #Dst ")"; \
129 static constexpr AssemblerFixup *Fixup = nullptr; \
129 if (GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_esp && \ 130 if (GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_esp && \
130 GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_ebp) { \ 131 GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_ebp) { \
131 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Base, \ 132 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Base, \
132 Immediate(BaseValue)); \ 133 Immediate(BaseValue)); \
133 } \ 134 } \
134 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst, \ 135 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst, \
135 Address(GPRRegister::Encoded_Reg_##Base, Disp)); \ 136 Address(GPRRegister::Encoded_Reg_##Base, Disp, Fixup)); \
136 AssembledTest test = assemble(); \ 137 AssembledTest test = assemble(); \
137 test.run(); \ 138 test.run(); \
138 ASSERT_EQ(test.Base() + (Disp), test.Dst()) << TestString << " with Disp " \ 139 ASSERT_EQ(test.Base() + (Disp), test.Dst()) << TestString << " with Disp " \
139 << Disp; \ 140 << Disp; \
140 reset(); \ 141 reset(); \
141 } while (0) 142 } while (0)
142 143
143 #define TestLeaIndex32bitDisp(Index, IndexValue, Disp, Dst0, Dst1, Dst2, Dst3) \ 144 #define TestLeaIndex32bitDisp(Index, IndexValue, Disp, Dst0, Dst1, Dst2, Dst3) \
144 do { \ 145 do { \
145 static constexpr char TestString[] = \ 146 static constexpr char TestString[] = \
146 "(" #Index ", " #IndexValue ", " #Dst0 ", " #Dst1 ", " #Dst2 \ 147 "(" #Index ", " #IndexValue ", " #Dst0 ", " #Dst1 ", " #Dst2 \
147 ", " #Dst3 ")"; \ 148 ", " #Dst3 ")"; \
149 static constexpr AssemblerFixup *Fixup = nullptr; \
148 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Index, \ 150 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Index, \
149 Immediate(IndexValue)); \ 151 Immediate(IndexValue)); \
150 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst0, \ 152 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst0, \
151 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_1, Disp)); \ 153 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_1, Disp, \
154 Fixup)); \
152 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \ 155 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \
153 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_2, Disp)); \ 156 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_2, Disp, \
157 Fixup)); \
154 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst2, \ 158 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst2, \
155 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_4, Disp)); \ 159 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_4, Disp, \
160 Fixup)); \
156 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst3, \ 161 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst3, \
157 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_8, Disp)); \ 162 Address(GPRRegister::Encoded_Reg_##Index, Traits::TIMES_8, Disp, \
163 Fixup)); \
158 AssembledTest test = assemble(); \ 164 AssembledTest test = assemble(); \
159 test.run(); \ 165 test.run(); \
160 ASSERT_EQ((test.Index() << Traits::TIMES_1) + (Disp), test.Dst0()) \ 166 ASSERT_EQ((test.Index() << Traits::TIMES_1) + (Disp), test.Dst0()) \
161 << TestString << " " << Disp; \ 167 << TestString << " " << Disp; \
162 ASSERT_EQ((test.Index() << Traits::TIMES_2) + (Disp), test.Dst1()) \ 168 ASSERT_EQ((test.Index() << Traits::TIMES_2) + (Disp), test.Dst1()) \
163 << TestString << " " << Disp; \ 169 << TestString << " " << Disp; \
164 ASSERT_EQ((test.Index() << Traits::TIMES_4) + (Disp), test.Dst2()) \ 170 ASSERT_EQ((test.Index() << Traits::TIMES_4) + (Disp), test.Dst2()) \
165 << TestString << " " << Disp; \ 171 << TestString << " " << Disp; \
166 ASSERT_EQ((test.Index() << Traits::TIMES_8) + (Disp), test.Dst3()) \ 172 ASSERT_EQ((test.Index() << Traits::TIMES_8) + (Disp), test.Dst3()) \
167 << TestString << " " << Disp; \ 173 << TestString << " " << Disp; \
168 reset(); \ 174 reset(); \
169 } while (0) 175 } while (0)
170 176
171 #define TestLeaBaseIndexDisp(Base, BaseValue, Index, IndexValue, Disp, Dst0, \ 177 #define TestLeaBaseIndexDisp(Base, BaseValue, Index, IndexValue, Disp, Dst0, \
172 Dst1, Dst2, Dst3) \ 178 Dst1, Dst2, Dst3) \
173 do { \ 179 do { \
174 static constexpr char TestString[] = \ 180 static constexpr char TestString[] = \
175 "(" #Base ", " #BaseValue ", " #Index ", " #IndexValue ", " #Dst0 \ 181 "(" #Base ", " #BaseValue ", " #Index ", " #IndexValue ", " #Dst0 \
176 ", " #Dst1 ", " #Dst2 ", " #Dst3 ")"; \ 182 ", " #Dst1 ", " #Dst2 ", " #Dst3 ")"; \
183 static constexpr AssemblerFixup *Fixup = nullptr; \
177 if (GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_esp && \ 184 if (GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_esp && \
178 GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_ebp) { \ 185 GPRRegister::Encoded_Reg_##Base != GPRRegister::Encoded_Reg_ebp) { \
179 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Base, \ 186 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Base, \
180 Immediate(BaseValue)); \ 187 Immediate(BaseValue)); \
181 } \ 188 } \
182 /* esp is not a valid index register. */ \ 189 /* esp is not a valid index register. */ \
183 if (GPRRegister::Encoded_Reg_##Index != GPRRegister::Encoded_Reg_ebp) { \ 190 if (GPRRegister::Encoded_Reg_##Index != GPRRegister::Encoded_Reg_ebp) { \
184 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Index, \ 191 __ mov(IceType_i32, GPRRegister::Encoded_Reg_##Index, \
185 Immediate(IndexValue)); \ 192 Immediate(IndexValue)); \
186 } \ 193 } \
187 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst0, \ 194 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst0, \
188 Address(GPRRegister::Encoded_Reg_##Base, \ 195 Address(GPRRegister::Encoded_Reg_##Base, \
189 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_1, Disp)); \ 196 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_1, Disp, \
197 Fixup)); \
190 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \ 198 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst1, \
191 Address(GPRRegister::Encoded_Reg_##Base, \ 199 Address(GPRRegister::Encoded_Reg_##Base, \
192 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_2, Disp)); \ 200 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_2, Disp, \
201 Fixup)); \
193 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst2, \ 202 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst2, \
194 Address(GPRRegister::Encoded_Reg_##Base, \ 203 Address(GPRRegister::Encoded_Reg_##Base, \
195 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_4, Disp)); \ 204 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_4, Disp, \
205 Fixup)); \
196 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst3, \ 206 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst3, \
197 Address(GPRRegister::Encoded_Reg_##Base, \ 207 Address(GPRRegister::Encoded_Reg_##Base, \
198 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_8, Disp)); \ 208 GPRRegister::Encoded_Reg_##Index, Traits::TIMES_8, Disp, \
209 Fixup)); \
199 AssembledTest test = assemble(); \ 210 AssembledTest test = assemble(); \
200 test.run(); \ 211 test.run(); \
201 uint32_t ExpectedIndexValue = test.Index(); \ 212 uint32_t ExpectedIndexValue = test.Index(); \
202 if (GPRRegister::Encoded_Reg_##Index == GPRRegister::Encoded_Reg_esp) { \ 213 if (GPRRegister::Encoded_Reg_##Index == GPRRegister::Encoded_Reg_esp) { \
203 ExpectedIndexValue = 0; \ 214 ExpectedIndexValue = 0; \
204 } \ 215 } \
205 ASSERT_EQ(test.Base() + (ExpectedIndexValue << Traits::TIMES_1) + (Disp), \ 216 ASSERT_EQ(test.Base() + (ExpectedIndexValue << Traits::TIMES_1) + (Disp), \
206 test.Dst0()) \ 217 test.Dst0()) \
207 << TestString << " " << Disp; \ 218 << TestString << " " << Disp; \
208 ASSERT_EQ(test.Base() + (ExpectedIndexValue << Traits::TIMES_2) + (Disp), \ 219 ASSERT_EQ(test.Base() + (ExpectedIndexValue << Traits::TIMES_2) + (Disp), \
(...skipping 70 matching lines...) Expand 10 before | Expand all | Expand 10 after
279 // by the assembler has different meanings in x86-32 and x86-64. 290 // by the assembler has different meanings in x86-32 and x86-64.
280 #undef TestLeaBaseIndexDisp 291 #undef TestLeaBaseIndexDisp
281 #undef TestLeaScaled32bitDisp 292 #undef TestLeaScaled32bitDisp
282 #undef TestLeaBaseDisp 293 #undef TestLeaBaseDisp
283 } 294 }
284 295
285 TEST_F(AssemblerX8632LowLevelTest, LeaAbsolute) { 296 TEST_F(AssemblerX8632LowLevelTest, LeaAbsolute) {
286 #define TestLeaAbsolute(Dst, Value) \ 297 #define TestLeaAbsolute(Dst, Value) \
287 do { \ 298 do { \
288 static constexpr char TestString[] = "(" #Dst ", " #Value ")"; \ 299 static constexpr char TestString[] = "(" #Dst ", " #Value ")"; \
289 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst, \ 300 static constexpr AssemblerFixup *Fixup = nullptr; \
290 Address(Address::ABSOLUTE, Value)); \ 301 __ lea(IceType_i32, GPRRegister::Encoded_Reg_##Dst, Address(Value, Fixup));\
291 static constexpr uint32_t ByteCount = 6; \ 302 static constexpr uint32_t ByteCount = 6; \
292 ASSERT_EQ(ByteCount, codeBytesSize()) << TestString; \ 303 ASSERT_EQ(ByteCount, codeBytesSize()) << TestString; \
293 static constexpr uint8_t Opcode = 0x8D; \ 304 static constexpr uint8_t Opcode = 0x8D; \
294 static constexpr uint8_t ModRM = \ 305 static constexpr uint8_t ModRM = \
295 /*mod=*/0x00 | /*reg*/ (GPRRegister::Encoded_Reg_##Dst << 3) | \ 306 /*mod=*/0x00 | /*reg*/ (GPRRegister::Encoded_Reg_##Dst << 3) | \
296 /*rm*/ GPRRegister::Encoded_Reg_ebp; \ 307 /*rm*/ GPRRegister::Encoded_Reg_ebp; \
297 verifyBytes<ByteCount>(codeBytes(), Opcode, ModRM, (Value)&0xFF, \ 308 verifyBytes<ByteCount>(codeBytes(), Opcode, ModRM, (Value)&0xFF, \
298 (Value >> 8) & 0xFF, (Value >> 16) & 0xFF, \ 309 (Value >> 8) & 0xFF, (Value >> 16) & 0xFF, \
299 (Value >> 24) & 0xFF); \ 310 (Value >> 24) & 0xFF); \
300 reset(); \ 311 reset(); \
(...skipping 1574 matching lines...) Expand 10 before | Expand all | Expand 10 after
1875 #undef TestImplValue 1886 #undef TestImplValue
1876 #undef TestImplSize 1887 #undef TestImplSize
1877 #undef TestImplRegAddr 1888 #undef TestImplRegAddr
1878 #undef TestImplRegReg 1889 #undef TestImplRegReg
1879 } 1890 }
1880 1891
1881 } // end of anonymous namespace 1892 } // end of anonymous namespace
1882 } // end of namespace Test 1893 } // end of namespace Test
1883 } // end of namespace X8632 1894 } // end of namespace X8632
1884 } // end of namespace Ice 1895 } // end of namespace Ice
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