| OLD | NEW |
| 1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8664Traits.h - x86-64 traits -*- C++ -*-=// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
| (...skipping 183 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 194 Address() = delete; | 194 Address() = delete; |
| 195 | 195 |
| 196 public: | 196 public: |
| 197 Address(const Address &other) : Operand(other) {} | 197 Address(const Address &other) : Operand(other) {} |
| 198 | 198 |
| 199 Address &operator=(const Address &other) { | 199 Address &operator=(const Address &other) { |
| 200 Operand::operator=(other); | 200 Operand::operator=(other); |
| 201 return *this; | 201 return *this; |
| 202 } | 202 } |
| 203 | 203 |
| 204 Address(GPRRegister base, int32_t disp) { | 204 Address(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) { |
| 205 if (disp == 0 && (base & 7) != RegX8664::Encoded_Reg_ebp) { | 205 if (Fixup == nullptr && Disp == 0 && |
| 206 SetModRM(0, base); | 206 (Base & 7) != RegX8664::Encoded_Reg_ebp) { |
| 207 if ((base & 7) == RegX8664::Encoded_Reg_esp) | 207 SetModRM(0, Base); |
| 208 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base); | 208 if ((Base & 7) == RegX8664::Encoded_Reg_esp) |
| 209 } else if (Utils::IsInt(8, disp)) { | 209 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, Base); |
| 210 SetModRM(1, base); | 210 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
| 211 if ((base & 7) == RegX8664::Encoded_Reg_esp) | 211 SetModRM(1, Base); |
| 212 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base); | 212 if ((Base & 7) == RegX8664::Encoded_Reg_esp) |
| 213 SetDisp8(disp); | 213 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, Base); |
| 214 SetDisp8(Disp); |
| 214 } else { | 215 } else { |
| 215 SetModRM(2, base); | 216 SetModRM(2, Base); |
| 216 if ((base & 7) == RegX8664::Encoded_Reg_esp) | 217 if ((Base & 7) == RegX8664::Encoded_Reg_esp) |
| 217 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, base); | 218 SetSIB(TIMES_1, RegX8664::Encoded_Reg_esp, Base); |
| 218 SetDisp32(disp); | 219 SetDisp32(Disp); |
| 220 if (Fixup) |
| 221 SetFixup(Fixup); |
| 219 } | 222 } |
| 220 } | 223 } |
| 221 | 224 |
| 222 Address(GPRRegister index, ScaleFactor scale, int32_t disp) { | 225 Address(GPRRegister Index, ScaleFactor Scale, int32_t Disp, |
| 223 assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode. | 226 AssemblerFixup *Fixup) { |
| 227 assert(Index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode. |
| 224 SetModRM(0, RegX8664::Encoded_Reg_esp); | 228 SetModRM(0, RegX8664::Encoded_Reg_esp); |
| 225 SetSIB(scale, index, RegX8664::Encoded_Reg_ebp); | 229 SetSIB(Scale, Index, RegX8664::Encoded_Reg_ebp); |
| 226 SetDisp32(disp); | 230 SetDisp32(Disp); |
| 231 if (Fixup) |
| 232 SetFixup(Fixup); |
| 227 } | 233 } |
| 228 | 234 |
| 229 Address(GPRRegister base, GPRRegister index, ScaleFactor scale, | 235 Address(GPRRegister Base, GPRRegister Index, ScaleFactor Scale, |
| 230 int32_t disp) { | 236 int32_t Disp, AssemblerFixup *Fixup) { |
| 231 assert(index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode. | 237 assert(Index != RegX8664::Encoded_Reg_esp); // Illegal addressing mode. |
| 232 if (disp == 0 && (base & 7) != RegX8664::Encoded_Reg_ebp) { | 238 if (Fixup == nullptr && Disp == 0 && |
| 239 (Base & 7) != RegX8664::Encoded_Reg_ebp) { |
| 233 SetModRM(0, RegX8664::Encoded_Reg_esp); | 240 SetModRM(0, RegX8664::Encoded_Reg_esp); |
| 234 SetSIB(scale, index, base); | 241 SetSIB(Scale, Index, Base); |
| 235 } else if (Utils::IsInt(8, disp)) { | 242 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
| 236 SetModRM(1, RegX8664::Encoded_Reg_esp); | 243 SetModRM(1, RegX8664::Encoded_Reg_esp); |
| 237 SetSIB(scale, index, base); | 244 SetSIB(Scale, Index, Base); |
| 238 SetDisp8(disp); | 245 SetDisp8(Disp); |
| 239 } else { | 246 } else { |
| 240 SetModRM(2, RegX8664::Encoded_Reg_esp); | 247 SetModRM(2, RegX8664::Encoded_Reg_esp); |
| 241 SetSIB(scale, index, base); | 248 SetSIB(Scale, Index, Base); |
| 242 SetDisp32(disp); | 249 SetDisp32(Disp); |
| 250 if (Fixup) |
| 251 SetFixup(Fixup); |
| 243 } | 252 } |
| 244 } | 253 } |
| 245 | 254 |
| 246 // PcRelTag is a special tag for requesting rip-relative addressing in | 255 /// Generate a RIP-relative address expression on x86-64. |
| 247 // X86-64. | 256 Address(RelocOffsetT Offset, AssemblerFixup *Fixup) { |
| 248 // TODO(jpp): this is bogus. remove. | |
| 249 enum AbsoluteTag { ABSOLUTE }; | |
| 250 | |
| 251 Address(AbsoluteTag, const uintptr_t Addr) { | |
| 252 SetModRM(0, RegX8664::Encoded_Reg_ebp); | |
| 253 SetDisp32(Addr); | |
| 254 } | |
| 255 | |
| 256 // TODO(jpp): remove this. | |
| 257 static Address Absolute(const uintptr_t Addr) { | |
| 258 return Address(ABSOLUTE, Addr); | |
| 259 } | |
| 260 | |
| 261 Address(AbsoluteTag, RelocOffsetT Offset, AssemblerFixup *Fixup) { | |
| 262 SetModRM(0, RegX8664::Encoded_Reg_ebp); | 257 SetModRM(0, RegX8664::Encoded_Reg_ebp); |
| 263 // Use the Offset in the displacement for now. If we decide to process | 258 // Use the Offset in the displacement for now. If we decide to process |
| 264 // fixups later, we'll need to patch up the emitted displacement. | 259 // fixups later, we'll need to patch up the emitted displacement. |
| 265 SetDisp32(Offset); | 260 SetDisp32(Offset); |
| 266 SetFixup(Fixup); | 261 if (Fixup) |
| 267 } | 262 SetFixup(Fixup); |
| 268 | |
| 269 // TODO(jpp): remove this. | |
| 270 static Address Absolute(RelocOffsetT Offset, AssemblerFixup *Fixup) { | |
| 271 return Address(ABSOLUTE, Offset, Fixup); | |
| 272 } | 263 } |
| 273 | 264 |
| 274 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { | 265 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { |
| 275 // TODO(jpp): ??? | 266 // TODO(jpp): ??? |
| 276 AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm); | 267 AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm); |
| 277 const RelocOffsetT Offset = 4; | 268 const RelocOffsetT Offset = 4; |
| 278 return Address(ABSOLUTE, Offset, Fixup); | 269 return Address(Offset, Fixup); |
| 279 } | 270 } |
| 280 }; | 271 }; |
| 281 | 272 |
| 282 //---------------------------------------------------------------------------- | 273 //---------------------------------------------------------------------------- |
| 283 // __ ______ __ __ ______ ______ __ __ __ ______ | 274 // __ ______ __ __ ______ ______ __ __ __ ______ |
| 284 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ | 275 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ |
| 285 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ | 276 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ |
| 286 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ | 277 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ |
| 287 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ | 278 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ |
| 288 // | 279 // |
| (...skipping 459 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 748 | 739 |
| 749 } // end of namespace X86Internal | 740 } // end of namespace X86Internal |
| 750 | 741 |
| 751 namespace X8664 { | 742 namespace X8664 { |
| 752 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>; | 743 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8664>; |
| 753 } // end of namespace X8664 | 744 } // end of namespace X8664 |
| 754 | 745 |
| 755 } // end of namespace Ice | 746 } // end of namespace Ice |
| 756 | 747 |
| 757 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H | 748 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8664TRAITS_H |
| OLD | NEW |