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| 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// | 1 //===- subzero/src/IceTargetLoweringX8632Traits.h - x86-32 traits -*- C++ -*-=// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 175 Address() = delete; | 175 Address() = delete; |
| 176 | 176 |
| 177 public: | 177 public: |
| 178 Address(const Address &other) : Operand(other) {} | 178 Address(const Address &other) : Operand(other) {} |
| 179 | 179 |
| 180 Address &operator=(const Address &other) { | 180 Address &operator=(const Address &other) { |
| 181 Operand::operator=(other); | 181 Operand::operator=(other); |
| 182 return *this; | 182 return *this; |
| 183 } | 183 } |
| 184 | 184 |
| 185 Address(GPRRegister base, int32_t disp) { | 185 Address(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) { |
| 186 if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) { | 186 if (Fixup == nullptr && Disp == 0 && Base != RegX8632::Encoded_Reg_ebp) { |
| 187 SetModRM(0, base); | 187 SetModRM(0, Base); |
| 188 if (base == RegX8632::Encoded_Reg_esp) | 188 if (Base == RegX8632::Encoded_Reg_esp) |
| 189 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base); | 189 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, Base); |
| 190 } else if (Utils::IsInt(8, disp)) { | 190 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
| 191 SetModRM(1, base); | 191 SetModRM(1, Base); |
| 192 if (base == RegX8632::Encoded_Reg_esp) | 192 if (Base == RegX8632::Encoded_Reg_esp) |
| 193 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base); | 193 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, Base); |
| 194 SetDisp8(disp); | 194 SetDisp8(Disp); |
| 195 } else { | 195 } else { |
| 196 SetModRM(2, base); | 196 SetModRM(2, Base); |
| 197 if (base == RegX8632::Encoded_Reg_esp) | 197 if (Base == RegX8632::Encoded_Reg_esp) |
| 198 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, base); | 198 SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, Base); |
| 199 SetDisp32(disp); | 199 SetDisp32(Disp); |
| 200 if (Fixup) |
| 201 SetFixup(Fixup); |
| 200 } | 202 } |
| 201 } | 203 } |
| 202 | 204 |
| 203 Address(GPRRegister index, ScaleFactor scale, int32_t disp) { | 205 Address(GPRRegister Index, ScaleFactor Scale, int32_t Disp, |
| 204 assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode. | 206 AssemblerFixup *Fixup) { |
| 207 assert(Index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode. |
| 205 SetModRM(0, RegX8632::Encoded_Reg_esp); | 208 SetModRM(0, RegX8632::Encoded_Reg_esp); |
| 206 SetSIB(scale, index, RegX8632::Encoded_Reg_ebp); | 209 SetSIB(Scale, Index, RegX8632::Encoded_Reg_ebp); |
| 207 SetDisp32(disp); | 210 SetDisp32(Disp); |
| 211 if (Fixup) |
| 212 SetFixup(Fixup); |
| 208 } | 213 } |
| 209 | 214 |
| 210 Address(GPRRegister base, GPRRegister index, ScaleFactor scale, | 215 Address(GPRRegister Base, GPRRegister Index, ScaleFactor Scale, |
| 211 int32_t disp) { | 216 int32_t Disp, AssemblerFixup *Fixup) { |
| 212 assert(index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode. | 217 assert(Index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode. |
| 213 if (disp == 0 && base != RegX8632::Encoded_Reg_ebp) { | 218 if (Fixup == nullptr && Disp == 0 && Base != RegX8632::Encoded_Reg_ebp) { |
| 214 SetModRM(0, RegX8632::Encoded_Reg_esp); | 219 SetModRM(0, RegX8632::Encoded_Reg_esp); |
| 215 SetSIB(scale, index, base); | 220 SetSIB(Scale, Index, Base); |
| 216 } else if (Utils::IsInt(8, disp)) { | 221 } else if (Fixup == nullptr && Utils::IsInt(8, Disp)) { |
| 217 SetModRM(1, RegX8632::Encoded_Reg_esp); | 222 SetModRM(1, RegX8632::Encoded_Reg_esp); |
| 218 SetSIB(scale, index, base); | 223 SetSIB(Scale, Index, Base); |
| 219 SetDisp8(disp); | 224 SetDisp8(Disp); |
| 220 } else { | 225 } else { |
| 221 SetModRM(2, RegX8632::Encoded_Reg_esp); | 226 SetModRM(2, RegX8632::Encoded_Reg_esp); |
| 222 SetSIB(scale, index, base); | 227 SetSIB(Scale, Index, Base); |
| 223 SetDisp32(disp); | 228 SetDisp32(Disp); |
| 229 if (Fixup) |
| 230 SetFixup(Fixup); |
| 224 } | 231 } |
| 225 } | 232 } |
| 226 | 233 |
| 227 /// AbsoluteTag is a special tag used by clients to create an absolute | 234 /// Generate an absolute address expression on x86-32. |
| 228 /// Address. | 235 Address(RelocOffsetT Offset, AssemblerFixup *Fixup) { |
| 229 enum AbsoluteTag { ABSOLUTE }; | |
| 230 | |
| 231 Address(AbsoluteTag, const uintptr_t Addr) { | |
| 232 SetModRM(0, RegX8632::Encoded_Reg_ebp); | |
| 233 SetDisp32(Addr); | |
| 234 } | |
| 235 | |
| 236 // TODO(jpp): remove this. | |
| 237 static Address Absolute(const uintptr_t Addr) { | |
| 238 return Address(ABSOLUTE, Addr); | |
| 239 } | |
| 240 | |
| 241 Address(AbsoluteTag, RelocOffsetT Offset, AssemblerFixup *Fixup) { | |
| 242 SetModRM(0, RegX8632::Encoded_Reg_ebp); | 236 SetModRM(0, RegX8632::Encoded_Reg_ebp); |
| 243 // Use the Offset in the displacement for now. If we decide to process | 237 // Use the Offset in the displacement for now. If we decide to process |
| 244 // fixups later, we'll need to patch up the emitted displacement. | 238 // fixups later, we'll need to patch up the emitted displacement. |
| 245 SetDisp32(Offset); | 239 SetDisp32(Offset); |
| 246 SetFixup(Fixup); | 240 if (Fixup) |
| 247 } | 241 SetFixup(Fixup); |
| 248 | |
| 249 // TODO(jpp): remove this. | |
| 250 static Address Absolute(RelocOffsetT Offset, AssemblerFixup *Fixup) { | |
| 251 return Address(ABSOLUTE, Offset, Fixup); | |
| 252 } | 242 } |
| 253 | 243 |
| 254 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { | 244 static Address ofConstPool(Assembler *Asm, const Constant *Imm) { |
| 255 AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm); | 245 AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm); |
| 256 const RelocOffsetT Offset = 0; | 246 const RelocOffsetT Offset = 0; |
| 257 return Address(ABSOLUTE, Offset, Fixup); | 247 return Address(Offset, Fixup); |
| 258 } | 248 } |
| 259 }; | 249 }; |
| 260 | 250 |
| 261 //---------------------------------------------------------------------------- | 251 //---------------------------------------------------------------------------- |
| 262 // __ ______ __ __ ______ ______ __ __ __ ______ | 252 // __ ______ __ __ ______ ______ __ __ __ ______ |
| 263 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ | 253 // /\ \ /\ __ \/\ \ _ \ \/\ ___\/\ == \/\ \/\ "-.\ \/\ ___\ |
| 264 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ | 254 // \ \ \___\ \ \/\ \ \ \/ ".\ \ \ __\\ \ __<\ \ \ \ \-. \ \ \__ \ |
| 265 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ | 255 // \ \_____\ \_____\ \__/".~\_\ \_____\ \_\ \_\ \_\ \_\\"\_\ \_____\ |
| 266 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ | 256 // \/_____/\/_____/\/_/ \/_/\/_____/\/_/ /_/\/_/\/_/ \/_/\/_____/ |
| 267 // | 257 // |
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| 741 | 731 |
| 742 } // end of namespace X86Internal | 732 } // end of namespace X86Internal |
| 743 | 733 |
| 744 namespace X8632 { | 734 namespace X8632 { |
| 745 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>; | 735 using Traits = ::Ice::X86Internal::MachineTraits<TargetX8632>; |
| 746 } // end of namespace X8632 | 736 } // end of namespace X8632 |
| 747 | 737 |
| 748 } // end of namespace Ice | 738 } // end of namespace Ice |
| 749 | 739 |
| 750 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H | 740 #endif // SUBZERO_SRC_ICETARGETLOWERINGX8632TRAITS_H |
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