Adds support for debugger API on MIPS.

runtime/vm/assembler_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/runtime_entry.h"
 #include "vm/simulator.h"
@@ skipping 313 matching lines @@
   addu(result, result, TMP1);
   lw(result, Address(result));
 }
 
 
 void Assembler::EnterStubFrame(bool uses_pp) {
   if (uses_pp) {
     addiu(SP, SP, Immediate(-4 * kWordSize));
     sw(ZR, Address(SP, 3 * kWordSize));  // PC marker is 0 in stubs.
     sw(RA, Address(SP, 2 * kWordSize));
-    sw(PP, Address(SP, 1 * kWordSize));
-    sw(FP, Address(SP, 0 * kWordSize));
-    mov(FP, SP);
+    sw(FP, Address(SP, 1 * kWordSize));
+    sw(PP, Address(SP, 0 * kWordSize));
+    addiu(FP, SP, Immediate(1 * kWordSize));
     // Setup pool pointer for this stub.
     Label next;
     bal(&next);
     delay_slot()->mov(T0, RA);
 
     const intptr_t object_pool_pc_dist =
         Instructions::HeaderSize() - Instructions::object_pool_offset() +
         CodeSize();
 
     Bind(&next);
     lw(PP, Address(T0, -object_pool_pc_dist));
   } else {
     addiu(SP, SP, Immediate(-3 * kWordSize));
     sw(ZR, Address(SP, 2 * kWordSize));  // PC marker is 0 in stubs.
     sw(RA, Address(SP, 1 * kWordSize));
     sw(FP, Address(SP, 0 * kWordSize));
     mov(FP, SP);
   }
 }
 
 
 void Assembler::LeaveStubFrame(bool uses_pp) {
-  mov(SP, FP);
   if (uses_pp) {
+    addiu(SP, FP, Immediate(-1 * kWordSize));
     lw(RA, Address(SP, 2 * kWordSize));
-    lw(PP, Address(SP, 1 * kWordSize));
-    lw(FP, Address(SP, 0 * kWordSize));
+    lw(FP, Address(SP, 1 * kWordSize));
+    lw(PP, Address(SP, 0 * kWordSize));
     addiu(SP, SP, Immediate(4 * kWordSize));
   } else {
+    mov(SP, FP);
     lw(RA, Address(SP, 1 * kWordSize));
     lw(FP, Address(SP, 0 * kWordSize));
     addiu(SP, SP, Immediate(3 * kWordSize));
   }
 }
 
 
 void Assembler::CallRuntime(const RuntimeEntry& entry) {
   entry.Call(this);
 }
@@ skipping 66 matching lines @@
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
+  TraceSimMsg("EnterCallRuntimeFrame");
+
   if (prologue_offset_ == -1) {
     prologue_offset_ = CodeSize();
   }
 
   // Save volatile CPU and FPU registers on the stack:
   // -------------
   // FPU Registers
   // CPU Registers
   // RA
   // FP
@@ skipping 22 matching lines @@
   ReserveAlignedFrameSpace(frame_space);
 }
 
 
 void Assembler::LeaveCallRuntimeFrame() {
   const intptr_t kPushedRegistersSize =
       kDartVolatileCpuRegCount * kWordSize +
       2 * kWordSize +  // FP and RA.
       kDartVolatileFpuRegCount * kWordSize;
 
+  TraceSimMsg("LeaveCallRuntimeFrame");
+
   // SP might have been modified to reserve space for arguments
   // and ensure proper alignment of the stack frame.
   // We need to restore it before restoring registers.
   mov(SP, FP);
 
   // Restore volatile CPU and FPU registers from the stack.
   lw(FP, Address(SP, 0 * kWordSize));
   lw(RA, Address(SP, 1 * kWordSize));
   for (int i = kDartFirstVolatileCpuReg; i <= kDartLastVolatileCpuReg; i++) {
     // + 2 because FP goes in slot 0.
@@ skipping 49 matching lines @@
     Emit(reinterpret_cast<int32_t>(message));
     Bind(&msg);
     break_(Instr::kMsgMessageCode);
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS