Subzero: Refactor x86 register representation to actively use aliases.

src/IceTargetLoweringX86RegClass.h

Index: src/IceTargetLoweringX86RegClass.h
diff --git a/src/IceTargetLoweringX86RegClass.h b/src/IceTargetLoweringX86RegClass.h
new file mode 100644
index 0000000000000000000000000000000000000000..35ae316596b06c6df89ed94a781499a0968812c9
--- /dev/null
+++ b/src/IceTargetLoweringX86RegClass.h
@@ -0,0 +1,36 @@
+//===- subzero/src/IceTargetLoweringX86RegClass.h - x86 reg class -*- C++ -*-=//
+//
+//                        The Subzero Code Generator
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file declares the X86 register class extensions.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H
+#define SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H
+
+#include "IceOperand.h" // RC_Target
+
+namespace Ice {
+namespace X86Internal {
+
+// Extend enum RegClass with x86-specific register classes.
+enum RegClassX86 : uint8_t {
+  RCX86_Is64To8 = RC_Target, // 64-bit GPR trivially truncable to 8-bit
+  RCX86_Is32To8,             // 32-bit GPR trivially truncable to 8-bit
+  RCX86_Is16To8,             // 16-bit GPR trivially truncable to 8-bit
+  RCX86_IsTrunc8Rcvr,        // 8-bit GPR that can receive a trunc operation
+  RCX86_IsAhRcvr,            // 8-bit GPR that can be a mov dest from %ah
+  RCX86_NUM
+};
+
+} // end of namespace X86Internal
+} // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX86REGCLASS_H