Index: src/IceTargetLoweringX8632Traits.h |
diff --git a/src/IceTargetLoweringX8632Traits.h b/src/IceTargetLoweringX8632Traits.h |
index 1c92bedae9c679635387dba03c6485e2df4bd156..cd2670207e6a71deb4ca5a6b9cbd9617d25c7ab5 100644 |
--- a/src/IceTargetLoweringX8632Traits.h |
+++ b/src/IceTargetLoweringX8632Traits.h |
@@ -22,8 +22,9 @@ |
#include "IceInstX8632.def" |
#include "IceOperand.h" |
#include "IceRegistersX8632.h" |
-#include "IceTargetLoweringX8632.def" |
#include "IceTargetLowering.h" |
+#include "IceTargetLoweringX8632.def" |
+#include "IceTargetLoweringX86RegClass.h" |
#include <array> |
@@ -398,7 +399,7 @@ template <> struct MachineTraits<TargetX8632> { |
} |
static void initRegisterSet( |
- std::array<llvm::SmallBitVector, IceType_NUM> *TypeToRegisterSet, |
+ std::array<llvm::SmallBitVector, RCX86_NUM> *TypeToRegisterSet, |
std::array<llvm::SmallBitVector, RegisterSet::Reg_NUM> *RegisterAliases, |
llvm::SmallBitVector *ScratchRegs) { |
llvm::SmallBitVector IntegerRegistersI32(RegisterSet::Reg_NUM); |
@@ -406,6 +407,11 @@ template <> struct MachineTraits<TargetX8632> { |
llvm::SmallBitVector IntegerRegistersI8(RegisterSet::Reg_NUM); |
llvm::SmallBitVector FloatRegisters(RegisterSet::Reg_NUM); |
llvm::SmallBitVector VectorRegisters(RegisterSet::Reg_NUM); |
+ llvm::SmallBitVector Trunc64To8Registers(RegisterSet::Reg_NUM); |
+ llvm::SmallBitVector Trunc32To8Registers(RegisterSet::Reg_NUM); |
+ llvm::SmallBitVector Trunc16To8Registers(RegisterSet::Reg_NUM); |
+ llvm::SmallBitVector Trunc8RcvrRegisters(RegisterSet::Reg_NUM); |
+ llvm::SmallBitVector AhRcvrRegisters(RegisterSet::Reg_NUM); |
llvm::SmallBitVector InvalidRegisters(RegisterSet::Reg_NUM); |
ScratchRegs->resize(RegisterSet::Reg_NUM); |
#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \ |
@@ -416,6 +422,11 @@ template <> struct MachineTraits<TargetX8632> { |
(IntegerRegistersI8)[RegisterSet::val] = is8; \ |
(FloatRegisters)[RegisterSet::val] = isXmm; \ |
(VectorRegisters)[RegisterSet::val] = isXmm; \ |
+ (Trunc64To8Registers)[RegisterSet::val] = is64To8; \ |
+ (Trunc32To8Registers)[RegisterSet::val] = is32To8; \ |
+ (Trunc16To8Registers)[RegisterSet::val] = is16To8; \ |
+ (Trunc8RcvrRegisters)[RegisterSet::val] = isTrunc8Rcvr; \ |
+ (AhRcvrRegisters)[RegisterSet::val] = isAhRcvr; \ |
(*RegisterAliases)[RegisterSet::val].resize(RegisterSet::Reg_NUM); \ |
for (SizeT RegAlias : aliases) { \ |
assert(!(*RegisterAliases)[RegisterSet::val][RegAlias] && \ |
@@ -427,21 +438,26 @@ template <> struct MachineTraits<TargetX8632> { |
REGX8632_TABLE; |
#undef X |
- (*TypeToRegisterSet)[IceType_void] = InvalidRegisters; |
- (*TypeToRegisterSet)[IceType_i1] = IntegerRegistersI8; |
- (*TypeToRegisterSet)[IceType_i8] = IntegerRegistersI8; |
- (*TypeToRegisterSet)[IceType_i16] = IntegerRegistersI16; |
- (*TypeToRegisterSet)[IceType_i32] = IntegerRegistersI32; |
- (*TypeToRegisterSet)[IceType_i64] = IntegerRegistersI32; |
- (*TypeToRegisterSet)[IceType_f32] = FloatRegisters; |
- (*TypeToRegisterSet)[IceType_f64] = FloatRegisters; |
- (*TypeToRegisterSet)[IceType_v4i1] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v8i1] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v16i1] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v16i8] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v8i16] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v4i32] = VectorRegisters; |
- (*TypeToRegisterSet)[IceType_v4f32] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_void] = InvalidRegisters; |
+ (*TypeToRegisterSet)[RC_i1] = IntegerRegistersI8; |
+ (*TypeToRegisterSet)[RC_i8] = IntegerRegistersI8; |
+ (*TypeToRegisterSet)[RC_i16] = IntegerRegistersI16; |
+ (*TypeToRegisterSet)[RC_i32] = IntegerRegistersI32; |
+ (*TypeToRegisterSet)[RC_i64] = IntegerRegistersI32; |
+ (*TypeToRegisterSet)[RC_f32] = FloatRegisters; |
+ (*TypeToRegisterSet)[RC_f64] = FloatRegisters; |
+ (*TypeToRegisterSet)[RC_v4i1] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v8i1] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v16i1] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v16i8] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v8i16] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v4i32] = VectorRegisters; |
+ (*TypeToRegisterSet)[RC_v4f32] = VectorRegisters; |
+ (*TypeToRegisterSet)[RCX86_Is64To8] = Trunc64To8Registers; |
+ (*TypeToRegisterSet)[RCX86_Is32To8] = Trunc32To8Registers; |
+ (*TypeToRegisterSet)[RCX86_Is16To8] = Trunc16To8Registers; |
+ (*TypeToRegisterSet)[RCX86_IsTrunc8Rcvr] = Trunc8RcvrRegisters; |
+ (*TypeToRegisterSet)[RCX86_IsAhRcvr] = AhRcvrRegisters; |
} |
static llvm::SmallBitVector |
@@ -512,7 +528,12 @@ template <> struct MachineTraits<TargetX8632> { |
Index |= (is8 << (AttrKey++)); \ |
Index |= (is16 << (AttrKey++)); \ |
Index |= (is32 << (AttrKey++)); \ |
+ Index |= (is64 << (AttrKey++)); \ |
Index |= (isXmm << (AttrKey++)); \ |
+ Index |= (is16To8 << (AttrKey++)); \ |
+ Index |= (is32To8 << (AttrKey++)); \ |
+ Index |= (is64To8 << (AttrKey++)); \ |
+ Index |= (isTrunc8Rcvr << (AttrKey++)); \ |
/* val is assigned to an equivalence class based on its properties. */ \ |
EquivalenceClasses[Index].push_back(RegisterSet::val); \ |
} |